For a MIPI interface with 600 Mb/s per lane, 4 lanes, single pixel mode design, processing YUV420 8-bit data, the minimum required video clock is (600*4)/(1*8) or higher, where 8 is the number of bits in one 8-bit YUV420 pixel.
video_aclk1(MHz) = 600*4/(4*8) = 75 MHz video_aclk2(MHz) = 600*4/(1*8) = 300 MHz
The final video clock is:
video_aclk(MHz) = max{75 MHz,300 MHz} = 300 MHz
Note: Due to the internal data path architecture of the pixel processing
the minimum supported data type for line rates greater than 1500 Mb/s is RAW8. RAW6 and RAW7
data types are not supported for line rates greater
than 1500 Mb/s.