User Parameters - User Parameters - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document_ID
PG232
Release_Date
2026-07-08
Version
6.0 English

The following table shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).

Table 1. Vivado IDE Parameter to User Parameter Relationship
Vivado IDE Parameter User Parameter Default Value
Pixel Format CMN_PXL_FORMAT RAW8
YUV420 word count YUV420_BUF_DPTH 128
PHY MODE (C-PHY/D-PHY) C_PHY_MODE DPHY
Serial Data Lanes CMN_NUM_LANES 1
Allowed VC CMN_VC All
Pixels Per Clock CMN_NUM_PIXELS 1
Include video Format Bridge (VFB) CMN_INC_VFB true
Support MIPI ISP Bridge C_SPRT_ISP_BRIDGE false
Enable dynamic line rate switching C_EN_DYNAMIC_LINE_RATE false
Enable Deskew Detection 1 C_RCVE_DESKEW_SEQ false
Enable Alternate Deskew Detection 2 C_RCVE_ALT_DESKEW_SEQ false
Enable Preamble Deskew Detection 2 C_RCVE_PREAMBLE_SEQ false
Support CSI Spec V2_0 C_EN_CSI_V2_0 false
Support VCX Feature C_EN_VCX false
Line Rate (Mb/s) DPY_LINE_RATE 1000
D-PHY Register Interface DPY_EN_REG_IF false
Calibration Mode C_CAL_MODE None
Select IO Bank Type C_IO_TYPE HPIO
IDELAY Tap Value C_IDLY_TAP 1
External IDELAY tap loading C_EN_EXT_TAP false
Include IDELAYCTRL in Core C_SHARE_IDLYCTRL false
Enable 300 MHZ Clock for IDELAYCTRL C_EN_CLK300M false
Embedded non-image Interface CSI_EMB_NON_IMG false
Line Buffer Depth CSI_BUF_DEPTH 2048
Enable CRC C_CSI_EN_CRC true
Enable Active Lanes C_CSI_EN_ACTIVELANES false
Shared Logic Support Level 0
HP IO Bank Selection HP_IO_BANK_SELECTION Value based on part selected.
Clock Lane CLK_LANE_IO_LOC Value based on part selected
Data Lane0 DATA_LANE0_IO_LOC Value based on part selected
Data Lane1 DATA_LANE1_IO_LOC Value based on part selected
Data Lane2 DATA_LANE2_IO_LOC Value based on part selected
Data Lane3 DATA_LANE3_IO_LOC Value based on part selected
HS_SETTLE Parameter (ns) 3 C_HS_SETTLE_NS 135ns + 10UI
Filter User Defined data types C_CSI_FILTER_USERDATATYPE false
Target Board C_EXDES_BOARD ZCU102
FMC Model C_EXDES_FMC LI-IMX274MIPI-FMC V1.0 Single Sensor
Design Topology C_EXDES_CONFIG MIPI_Video_Pipe_Camera_to_Display
TDATA Width AXIS_TDATA_WIDTH 32
TDEST Width AXIS_TDEST_WIDTH 4
TUSER Width (CSI-2 options) AXIS_TUSER_WIDTH 96
TUSER Width (VFB options) VFB_TU_WIDTH 1
Internal MMCM C_EXT_MMCM 0
  1. Supported when the line rate exceeds 1500 Mb/s and PHY MODE is set to DPHY. Ensure these conditions are met before enabling these features.
  2. Supported only on Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices when the line rate exceeds 2500 Mb/s and PHY MODE is set to DPHY. Ensure these conditions are met before enabling these features.
  3. Hidden parameter, sets the HS_SETTLE value. Set through the Tcl flow.