Tclk-Post Requirement - Tclk-Post Requirement - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)
Document ID
PG232
Release Date
2025-11-20
Version
6.0 English

MIPI CSI-2 RX Subsystem needs Tclk-POST to be a minimum of 18 rxbyteclkhs. MIPI D-PHY v2.0 recommends the minimum value of Tclk-POST as 60 ns +52UI. For non-Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices, the system designer should consider the maximum of these two Tclk-POST values for the MIPI source.

For example,

  1. For a line rate of 896 Mb/s, rxbyteclkhs is 8.9285 ns. The required Tclk-POST is 18*8.9285 ns = 160 ns
  2. Examples for specific line rates are as follows.
Table 1. Line-rate Specific Example
Linerate EQ1: Tclk-POST minimum per D-PHY 2.0 specification (60 ns +52UI) EQ2:Required Tclk-POST minimum by MIPI CSI-2 RX Subsystem Final Tclk-POST MAX(EQ1, EQ2)
896 118 ns 160 ns 160 ns
1440 96 ns 100 ns 100 ns
2000 86 ns 72 ns 86 ns

Tclk-POST is the Transmitter (D-PHY or CSI-2) setting that the system designer must set based on the receiver requirements.