The following table describes the MIPI CSI-2 RX Subsystem I/O signals.
| Signal Name | Direction | Description |
|---|---|---|
| lite_aclk | I | AXI clock. |
| lite_aresetn | I | AXI reset. Active-Low. This signal needs to be synchronous to lite_aclk. |
| S00_AXI* | - | AXI4-Lite interface, defined in the Vivado Design Suite: AXI Reference Guide (UG1037) |
| dphy_clk_200M | I | Clock for PHY core. Must be 200 MHz. |
| video_aclk | I | Subsystem clock. |
| video_aresetn | I | Subsystem reset. Active-Low. This signal needs to be synchronous to video_aclk. |
| AXI4-Stream Video Interface when Video Format Bridge is Present | ||
| video_out_tvalid | O | Data valid. |
| video_out_tready | I | Slave ready to accept the data. |
| video_out_tuser[n-1:0] | O | n is based on TUSER width selected
in the Vivado IDE.
|
| video_out_tlast | O | End of line. |
| video_out_tdata[n-1:0] | O | Data n is based on the Data type and number of pixels selected in the Vivado IDE (refer to video_out Port Width). |
| video_out_tdest[0-10] 1 | O |
|
| AXI4-Stream Interface when Embedded Non-image Interface is Selected | ||
| emb_nonimg_tdata[n-1:0] | O | Data. n is based on Data type selected in the Vivado IDE (refer to Embedded Non-Image AXI4-Stream Interface TDATA Widths). |
| emb_nonimg_tdest[3:0] | O | Specifies the Virtual Channel Identifier (VC) value of the embedded non-image packet. |
| emb_nonimg_tkeep[n/8-1:0] | O | Specifies valid bytes. |
| emb_nonimg_tlast | O | End of line. |
| emb_nonimg_tready | I | Slave ready to accept data. |
| emb_nonimg_tuser[112:0] | O |
|
| emb_nonimg_tvalid | O | Data valid. |
| MIPI ISP Bridge option is selected When DPHY selected | ||
| header_data[31:0] | O | Header Data
|
| header_valid | O | Header valid |
| MIPI ISP Bridge option is selected When CPHY selected | ||
| header_data[47:0] | O |
|
| header_valid | O | Header valid |
| AXI4-Stream Interface when Video Format Bridge is Not Present | ||
| video_out_tdata[n-1:0] | O | Data. n is based on TDATA width selected in the Vivado IDE. |
| video_out_tdest[n-1:0] | O | n is based on TDEST width selected
in the Vivado IDE:
|
| video_out_tkeep[n/8-1:0] | O | Specifies valid bytes. |
| video_out_tlast | O | End of line. |
| video_out_tready | I | Slave ready to accept data. |
| video_out_tuser[n-1:0] | O | n is based on TUSER width selected
in the Vivado IDE
|
| video_out_tvalid | O | Data valid. |
| Other Signals | ||
| csirxss_csi_irq | O | Interrupt (active-High) from CSI-2 RX Controller. |
| frame_rcvd_pulse_out 2 | O | High when the Frame End (FE) short packet is received for the frame_rcvd_pulse_out O current frame. |
| AMD 7 series FPGA | ||
| mipi_dphy_if | O | D-PHY interface. |
| rxbyteclkhs | O | PPI high-speed receive byte clock. |
| system_rst_out | O | Reset indication due to PLL reset (active-High). |
| dlyctrl_rdy_out | O | Ready signal output from IDEALYCTRL, stating delay values are adjusted as per VTC changes. |
| dlyctrl_rdy_in | I | Ready signal input to IDELAYCTRL. Refer to “Include IDELAYCTRL in Core” in the Configuration Tab for more details. |
| clk_300m | I | 300 MHz clock for IDELAYCTRL. |
| UltraScale+ and Versal Adaptive SoC Shared Logic Outside the Subsystem | ||
| mipi_phy_if | O | D-PHY interface. |
| bg<x>_pin<y>_nc | I | Inferred bitslice ports. The core infers bitslice0 of a nibble
for strobe propagation within the byte group; <x> indicates byte group
(0,1,2,3); <y> indicates bitslice0 position (0 for the lower nibble, 6 for the
upper nibble)
|
| clkoutphy_in | I | PHY serial clock. |
| pll_lock_in | I | PLL Lock indication. |
| rxbyteclkhs | O | PPI high-speed receive byte clock. |
| rxbyteclkhs_cnts_in | I | Continuous PPI high-speed receive byte clock for line rates > 1500 Mb/s. |
| ext_mmcm_clk_in | I | External MMCM clock when selected External MMCM for line rates >1500. |
| ext_mmcm_lock_in | I | External MMCM lock in when selected External MMCM for line rates > 1500. |
| ext_mmcm_clk_out | O | MMCM clock out when selected to use MMCM inside subsystem for line rates >1500. |
| ext_mmcm_lock_out | O | MMCM lock out when selected to use MMCM inside subsystem for line rates > 1500. |
| Versal Premium Series Gen 2 Outside Subsystem | ||
| mipi_phy_if/mipi_c_phy_if | O | PHY (D-PHY/C-PHY) interface. |
| shared_rxwordlckhs_in | I | PPI high-speed receive word clock. |
| cnts_rxworkclkhs_in | I | PPI high-speed receive continuous word clock. |
| shared_plllocked_in | I | PLL lock indication (active-High). |
| shared_pll_clkoutphy_in | I | PHY serial clock. |
| shared_pll_clkoutphy_90_in | I | 90 shift of the pll_clkoutphy. |
| iophy_intf_rdy | O | Indication of IO PHY reset sequence completion. |
| Versal Premium Series Gen 2 Inside Subsystem | ||
| mipi_phy_if/mipi_c_phy_if | O | PHY (D-PHY/C-PHY) interface. |
| clkoutphy_out | O | PHY serial clock. |
| rxwordlckhs_outt | O | PPI high-speed receive word clock. |
| cnts_rxworkclkhs_outt | O | PPI high-speed receive continuous word clock. |
| system_rst_out | O | Reset indication due to PLL reset (active-High). |
| pll_lock_out | O | PLL lock indication (active-High). |
| pll_clkoutphy_90_out | O | 90 shift of the pll_clkoutphy. |
| iophy_intf_rdy | O | Indication of IO PHY reset sequence completion. |
| CSI-2 Controller Register Interface Disabled | ||
| ctrl_core_en | I | Enable the core to receive and process packets. |
| active_lanes[1:0] | I | Active lanes. |
| ctrl_dis_in_prgs | O | Indicates the CSI-2 RX Controller core disable is in progress. |
| errsotsynchs_intr | O | Interrupt output indicating SoT synchronization completely failed. |
| errsoths_intr | O | Interrupt output indicating SoT error detected. |
| cl_stopstate_intr | O | High when clock lane is currently in stop state. |
| dl<n>_stopstate_intr | O | High when the lane module is currently in stop state. |
| crc_status_intr | O | High when the computed CRC code is different from the received CRC code. |
| ecc_status_intr[1:0] | O | Bit 1- High when ECC syndrome is
computed and two bits error is detected in the received packet header. Bit 0: High when ECC syndrome was computed and a single bit error in the packet header was detected and corrected |
| linebuffer_full | O | High when line buffer is full. |
|
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