The following MIPI CSI-2 RX Controller registers can be monitored to confirm reception of data packets:
- Packet count in Core Status register
- Data type and Byte count in Image Information registers
- Frame received bit in Interrupt Status register
No packets received by the MIPI CSI-2 Subsystem
- Possible causes
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- No packets received at MIPI DPHY level itself
- Frame end packets not received or not passed the ECC checks at MIPI CSI-2 RX Subsystem level
- Debug instructions
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- Verify MIPI DPHY packet count registers. If the packet counts at MIPI DPHY level are not getting reported, debug connections/paths from source to MIPI DPHY Input
- Verify MIPI CSI-2 RX Controller interrupt status register to see if any ECC errors getting reported. If there is frequent ECC 2-bit error getting reported means some of the packets are not getting processed by MIPI CSI-2 RX Controller.
Packets received by the MIPI CSI-2 Subsystem with PPI Level Errors (like SoT Error, SoT sync Error) and/or Controller level errors (like ECC 1-bit, ECC 2-bit, CRC)
- Possible causes
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- Lane position mismatch between source (sensor) and MIPI CSI-2 RX Subsystem.
- Noise detected by MIPI DPHY as a valid packet.
- Debug instructions
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- Verify that the lane positions of the source (sensor) and the MIPI CSI-2 RX Subsystem are matching. Lane0 holds first byte of the packet, Lane1 holds the next byte and so on.
- Verify that sensor TX output timing. If it does not meet MIPI specification, adjust the MIPI D-PHY RX HS_SETTLE setting. When subsequently processed by the MIPI CSI-2 RX Controller, these packets are reported as erroneous packets. Increase the HS_SETTLE value either through the MIPI DPHY registers or through the C_HS_SETTLE_NS parameter (hidden) available in MIPI CSI-2 RX Subsystem.