- Ensure MIPI DPHY and MIPI CSI-2 RX Controller cores are in the enable state by reading the registers.
- Ensure Incorrect Lane Configuration is not set in the MIPI CSI-2 RX Controller Interrupt Status register.
- Ensure that the output AXI4-Stream bandwidth is high enough to meet throughput demand.
- Ensure line buffer full condition is not set in the MIPI CSI-2 RX Controller Interrupt Status register. Core setting this bit implies that the input data rate is higher than the output data rate. Consider either decreasing input data rate (D-PHY Line rate) or increase output data rate (select the appropriate output pixel per Clock: Single, Dual, Quad).