Core Configuration Register - Core Configuration Register - 6.0 English - PG232

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)
Document ID
PG232
Release Date
2025-11-20
Version
6.0 English

The Core Configuration register is described in the following table and allows you to enable and disable the MIPI CSI-2 RX Controller core and apply a soft reset during core operation.

Table 1. Core Configuration Register (0x00)
Bits Name Reset Value Access Description
31–3 Reserved N/A N/A Reserved
1 Soft Reset 0x0 R/W

1: Resets the core

0: Takes core out of soft reset

All registers reset to their default value except the following:

  • Soft Reset bit (offset 0x00 bit[1])
  • Core Enable bit (offset 0x00 bit[0])
  • Active Lanes Configuration bit (offset 0x04 bit[1:0])
  • Global Interrupt Enable Register (offset 0x20)
  • Interrupt Enable Register (offset 0x28)

When this bit is set to 1, the following also occurs:

  • Shut down port is not asserted on the PPI lanes
  • Internal FIFOs (PPI, Packet, Generic Short Packet) are flushed
  • Control Finite State Machine (FSM) stops processing current packet. Any partially written packet to memory is marked as errored. This packet, when made available through the AXI4-Stream interface, reports the error on TUSER[1].
2 Full Reset 0x0 R/W Full Reset, that is, when asserted it resets the PHY controller & the CSI2 Controller.
Note: This Bit is applicable only for Versal Prime, Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2.
Note: On the system bring up if ISR is not clean please assert this bit.
0 Core Enable 0x1 R/W

1: Enables the core to receive and process packets

0: Disables the core for operation

When disabled:

  • Shuts down port assertion on the PPI lanes
  • Internal FIFOs (PPI, Packet, Generic Short Packet) are flushed

  • Control FSM stops processing current packet

    Any partially written packet to memory is marked as errored. This packet, when made available through the AXI4-Stream interface, reports the error on TUSER[1].
  1. The short packet and line buffer FIFO full conditions take a few clocks to reflect in the register clock domain from the core clock domain due to Clock Domain Crossing (CDC) blocks.