Configuration Tab - Configuration Tab - 6.0 English - PG232

The Configuration tab page provides core-related configuration parameters. The following figure shows the subsystem configuration screen.

Pixel Format

Select the Data Type (pixel format) per the CSI-2 protocol (RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RGB888, RGB666, RGB565, RGB555, RGB444, YUV422 8-bit, YUV422_10bit, YUV420_8bit). This selection is not considered by the subsystem when Include Video Format Bridge is disabled.

YUV420 word count

Select the maximum Y-line word count in bytes when YUV420 pixel format is selected.

Note: Ensure the Y-line word count of the incoming data is at least eight bytes less than the selected value to avoid the YUV420 WC Error interrupt.

Serial Data Lanes

Select the maximum number of D-PHY lanes for this subsystem instance. Values are 1, 2, 3, or 4.

The maximum number of C-PHY lane for this subsystem instance is 1, 2, or 3.

Include Video Format Bridge (VFB)

Include or exclude the Video Format Bridge core in the subsystem is present. When this option is disabled, the Pixel Format selection is not considered by the subsystem. You can configure the stream data width (TDATA) when this option is disabled.

Support MIPI ISP Bridge

Visible and enabled when the Include Video Format Bridge (VFB)" option is selected.

Enable dynamic line rate switching

For non-Versal AI Edge Series Gen 2 and non-Versal Prime Series Gen 2 devices, this option is disabled by default. The PHY Register Interface must be activated for the Dynamic Line Rate feature to function properly. To enable, set PHY MODE to CPHY, PHY Register interface ON and support level to Include Shared Logic in core- 1.

Support CSI Spec V2_0

Select to enable CSI V2.0 features (RAW16, RAW20 support, and VCX feature support). In Versal Premium Series Gen 2 devices, this option is enabled by default.

Support VCX Feature

Option to include or exclude VCX feature. In Versal Premium Series Gen 2 devices, this option is enabled by default.

Line Rate (Mb/s)

Enter a line rate value in megabits per second (Mb/s) within the valid range: 80–4500 Mb/s, based on the device selected. The Vivado IDE automatically limits the line rates based on the selected device. For details about family/device specific line rate support, refer to the data sheet for your device.

Select PHY MODE

Specify the PHY type as either CPHY and DPHY.

Note: Applicable only for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices.

D-PHY/RX PHY Register Interface

Select to enable the register interface for the MIPI D-PHY/RX PHY core.

Select IO Bank Type

Specify the IO type as XP5IO or HPIO.

Note: Applicable only for Spartan UltraScale+ devices.

Enable Deskew Detection

Select to enable the deskew sequence detection and center alignment of clock and data lanes in the MIPI D-PHY core.

Note: Applicable only for UltraScale+ devices with line rates above 1500 Mb/s.

Note: The MIPI D-PHY RX IP has specific periodic deskew length requirements. The minimum required length of the periodic pattern is 213 UI.

Calibration Mode

Select the calibration for 7 series MIPI D-PHY RX subsystem.

None

The Calibration Mode does not add the IDELAY2 primitive.

Fixed

The Calibration Mode sets IDELAYE2 TAP value set in the IDELAY Tap Value.

Auto

The Calibration Mode adds the IDELAYE2 primitive and tap value is configured by D-PHY RX IP based on received traffic and calibration algorithm.

External IDELAY tap loading

Enables the loading of IDELAY tap values through external ports for calibration in Fixed mode.

Note: Clock these ports through dphy_clk_200M.

IDELAY Tap Value

Select the IDELAY TAP value used for calibration in Fixed mode. Values 1–31.

Include IDELAYCTRL in core

Select to include IDELAYCTRL in core. Only available in FIXED and AUTO calibration modes.

• For multiple MIPI CSI-2 RX IP cores that are sharing single IO bank, select Include the IDELAYCTRL option in the IP for the auto calibration mode. Only one IDELAYCTRL is available per a single clock region.
• If multiple MIPI CSI-2 RX cores exist in single clock region, select this option for only one MIPI CSI-2 RX IP core.
• For the rest of MIPI CSI-2 RX cores, this option needs to be deselected.

Note: Applicable only for 7 series MIPI CSI-2 RX IP configurations.

Note: For 7 series in AUTO Mode, when there are multiple instances of DPHY and they share the IDELAY control Ready from one DPHY Instance to other DPHY Instance. The DPHY Instance which shares the IDELAY Controller Ready cannot have the Enable 300 MHz clock for IDELAYCTRL set to true.

Note: For 7 series, the IP core is tested and validated at a maximum frequency of 1250 Mb/s; 1500 Mb/s is available in the GUI only for testing.

IODELAY_GROUP Name

Select the IODELAY_GROUP Name for the IDELAYCTRL. All core instances in the same bank sharing IDELAYCTRL must have the same name for this parameter. Select a unique name per bank.

Note: Available only for 7 series configurations.

Enable 300 MHz clock for IDELAYCTRL

Select to enable external 300 MHz clock port. Only available in AUTO calibration mode. This 300 MHz port is used for connecting to IDELAYCTRL. When you disable this option, IDELAYCTRL uses 200 MHz clock (dphy_clk_200M).

CSI2 Controller Register Interface

Deselect to remove the MIPI CSI-2 RX Controller register interface. Disabling this option improves resource count. When the CSI-2 RX Controller register interface is disabled, the core allows enabling/disabling the core through external ports. Also, some key status information is made available as external ports of the core. Refer to Port Descriptions for details of ports available when this option is deselected.

Note: For Versal Premium Series Gen 2 devices, the CSI2 Controller Register Interface is included by default. You cannot disable this option.

Embedded non-image Interface

Select to process and offload embedded non-image CSI-2 packets (with data type code 0x12) using a separate AXI4-Stream interface. If deselected, such packets are not processed and are ignored by the CSI-2 RX controller.

Filter User Defined data types

Select to Filter user defined data types (0x30–0x37) and do not output on Image interface (unsupported ErrId ISR[8] is not set even if filtering is enabled). If deselected, such packets are processed and presented on image interface.

Line Buffer Depth

Depth of internal RAM used to accommodate throttling on the output video interface. Values are 128, 256, 512, 1024, 2048, 4096, 8192, or 16384. Set this to the lowest value possible (for example, 128), and it does not cause line buffer full condition.

Note: There is no throttling allowed on the input to the PPI. Lowest value only applicable for non-Versal AI Edge Series Gen 2 and non-Versal Prime Series Gen 2 devices. For the line buffer depth calculation for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices, refer Line Buffer Depth Calculation for Versal AI Edge Series Gen2 and Versal Prime Series Gen 2 Devices.

Pixels Per Clock

Select the number of pixels to output per clock on output interface. Values are 1 (single pixel), 2 (dual pixel), or 4 (quad pixel). In Versal Premium Series Gen 2 devices, the clocks on the output interface are 1 (single pixel), 2 (dual pixel), 4 (quad pixel) or 8 (octa pixel).

TUSER Width

Width of the sideband signal [TUSER] to report information like the line number, frame number, ECC, and CRC.

Allowed VC

For non-Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices, select the VC values to use while processing the packets. Values are All, 0–15. For Versal devices, select the VC values to be used to while processing the packets. Values are All, 0, 1, 2, or 3.

Enable CRC

When set, CRC computation is performed on the packet payload and any errors are reported.

Enable Active Lanes

When set, the core supports the dynamic configuration of the number of active lanes from the maximum number of lanes selected during core generation using the parameter Serial Data Lanes. For example, when Serial Data Lanes is set to 3, the number of active lanes can be programmed using the protocol configuration register to be 1, 2, or 3. The core reports an error when the active lanes setting is greater than the serial lanes setting through the interrupt status register, bit-21.