The subsystem clocks are described in the following table. Clock frequencies should be selected to match the throughput requirement of the downstream video pipe IP cores.
| Clock Name | Description |
|---|---|
| lite_aclk | AXI4-Lite clock used by the register interface of all IP cores in the subsystem. |
| video_aclk | Clock used as core clock for all IP cores in the subsystem. |
| dphy_clk_200M | See the MIPI D-PHY LogiCORE IP Product Guide (PG202) for information on this clock. |
| clkoutphy_out |
The
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| clkoutphy_in | The clkoutphy_in signal should be connected to the clkoutphy_out signal generated when the Include Shared logic in core option is selected. |
| rxbyteclkhs_cnts_out | The rxbyteclkhs_cnts_out is the continuous clock signal generated within the PLL with the same frequency as rxbyteclkhs when the Include Shared logic in core option is selected and line rates are greater than 1500 Mb/s. |
| rxbyteclkhs_cnts_in | The rxbyteclkhs_cnts_in signal should be connected to the rxbyteclkhs_cnts_out signal generated when the Include Shared logic in example design option is selected and line rates are greater than 1500 Mb/s. |
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| Clock Name | Description |
|---|---|
| lite_aclk | AXI4-Lite clock used by the register interface of all IP cores in the subsystem. |
| video_aclk | Clock used as core clock for all IP cores in the subsystem. |
| dphy_clk_200M | See the MIPI D-PHY LogiCORE IP Product Guide (PG202) for information on this clock. |
| rxwordclkhs_out | Recovered clock in case of C-PHY mode and clock from rx clock lane in case of
D-PHY mode. For D-PHY Mode: 25.000 – 281.25 MHz Derived from the line rate divided by 16. For C-PHY Mode: 57.14 – 321.4 MHz Derived from line rate: For Line Rates <=2250 its Line Rate /7. For line rates from >2250 its Line Rate/14 |
| clkoutphy_out | The clkoutphy_out signal is generated within the PLL when the Include Shared logic in core option is selected. When Deskew detection is enabled, the clockoutphy_out signal is generated with the same line rate same as the subsystem line rate |
| shared_pll_clkoutphy_in | This signal should be connected to the clkoutphy_out signal generated when the Include Shared logic in core option is selected. |
| shared_pll_clkoutphy_90_in | This signal should be connected to the 90 degreee shift of shared_pll_clkoutphy_in signal generated when the Include Shared logic in core option is selected. |
| shared_pll_clkoutphy_in | This signal generated when the Include Shared logic in core option is selected. |
| cnts_rxwordclkhs_out | The cnts_rxwordclkhs_out is the continuous clock signal generated within the PLL with the same frequency as rxwordclkhs_out when the Include Shared logic in core option is selected |