Example Design Software - 2.3 English - PG231

Video Processing Subsystem Product Guide (PG231)

Document ID
PG231
Release Date
2025-07-09
Version
2.3 English
The synthesizeable example design requires both the Vivado and AMD Vitis™ software platforms.

The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware. In the window, select Include bitstream, select an export directory and click OK.

The example design files are found in the following Vitis directory: <install_directory>/<release>/data/embeddedsw/XilinxProcessorIPLib/drivers/vprocss_v2_14/examples/

Perform the following to generate the elf file (executable and linkable file) from the Vitis software platform.

  1. Open the Vitis application, and select Get Started > Set Workspace.
    Generated by Your Tool
  2. Create the platform component. Select Embedded Development > Create Platform Component.
  3. Enter the component name and location, and click Next.
    Generated by Your Tool
  4. Browse and select the hardware design XSA file generated with Vivado.
    Generated by Your Tool
  5. Select the operating system, processor, and compiler.
    Generated by Your Tool
  6. Review the summary, and click Finish.
  7. After the platform component is created, navigate to the welcome panel. In Embedded Development > Create Embedded Application, select Create Empty Embedded Application.
    Generated by Your Tool
  8. Choose the component name and location, and click Next.
    Generated by Your Tool
  9. In the Hardware tab, select the required platform, and click Next.
    Generated by Your Tool
  10. From the list of available domains, select your domain.
    Generated by Your Tool
  11. (Optional) Add source files, review the summary, and click Finish.
  12. If you skipped the previous step, import the source files into the application component. Right-click Sources and select Import > Files.
    Generated by Your Tool
  13. Import the required files.
    Generated by Your Tool
  14. To build the project, select Flow > Build. When prompted for Platform build, click Yes.
    Generated by Your Tool
  15. After the build completes, check the Output folder for the .elf file.
    Generated by Your Tool
  16. To download the bitstream into the FPGA, select Vitis > Program Device.
  17. Ensure the Bitstream field shows the file generated by the Tcl script, and click Program.
    Note: If the programming is successful, the DONE LED on the board turns green.
  18. A terminal program (HyperTerminal or PuTTY) is required for UART communication. Open the program, choose the appropriate port, set the baud rate to 115200, and establish a serial port connection.
  19. In the Explorer panel, select and right-click xv_procss_example.
  20. Select Run As > Launch on Hardware (GDB).
  21. Select Binaries and Qualifier, and click OK.