CAN FD LogiCORE IP Product Guide (PG223) - 3.0 English - This document describes the architecture and features of the CAN FD controller core and the function of the various registers in the design. This version of the core supports the AXI interconnect. - PG223
Document ID
PG223
Release Date
2025-08-28
Version
3.0 English
Introduction
Features
Other Features
IP Facts
Overview
Navigating Content by Design Process
About the Core
Core Description
Object Layer (Logical Link Layer)
Transfer Layer (Medium Access Control Layer)
Licensing and Ordering
License Checkers
License Type
Product Specification
Standards
Performance
Resource Utilization
Port Descriptions
Register Space
Core Register Descriptions
Software Reset Register (Address Offset + 0x0000)
Mode Select Register (Address Offset + 0x0004)
Arbitration Phase (Nominal) Baud Rate Prescaler Register (Address Offset + 0x0008)
Arbitration Phase (Nominal) Bit Timing Register (Address Offset + 0x000C)
Error Count Register (Address Offset + 0x0010)
Error Status Register (Address Offset + 0x0014)
Status Register (Address Offset + 0x0018)
Interrupt Status Register (Address Offset + 0x001C)
Interrupt Enable Register (Address Offset + 0x0020)
Interrupt Clear Register (Address Offset + 0x0024)
Timestamp Register (Address Offset + 0x0028)
Data Phase Baud Rate Prescaler Register (Address Offset + 0x0088)
Data Phase Bit Timing Register (Address Offset + 0x008C)
TX Buffer Ready Request Register (Address Offset + 0x0090)
Interrupt Enable TX Buffer Ready Request Served/Cleared (Address Offset + 0x0094)
TX Buffer Cancel Request (Address Offset + 0x0098)
Interrupt Enable TX Buffer Cancellation Served/Cleared (Address Offset + 0x009C)
TX Event FIFO Status Register (Address Offset + 0x00A0)
TX Event FIFO Watermark Register (Address Offset + 0x00A4)
RX Buffer Control Status Register 0 (Address Offset + 0x00B0) (0 to 15 RX Mailbox Buffers)
RX Buffer Control Status Register 1 (Address Offset + 0x00B4) (16 to 31 RX Mailbox Buffers)
RX Buffer Control Status Register 2 (Address Offset + 0x00B8) (32 to 48 RX Mailbox Buffers)
Interrupt Enable RX Buffer Full Register 0 (Address Offset + 0x00C0)
Interrupt Enable RX Buffer Full Register 1 (Address Offset + 0x00C4)
Acceptance Filter (Control) Register (Address Offset + 0x00E0)
RX FIFO Status Register (Address Offset + 0x00E8)
RX FIFO Watermark Register (Address Offset + 00EC)
CAN FD TX Message Space Register Descriptions
TB*-ID Register (Address Offset + 0x0100, 0x0148 …)
TB*-DLC Register (Address Offset + 0x0104, 0x014C …)
TB*-DW0 Register (Address Offset + 0x0108,…, 0x0150,…)
TB*-DW1-15 Register (Address Offset + 0x010C …, 0x0154,…)
TX Event FIFO Status Register
CAN FD TXE Message Space
TXE FIFO TB* ID Register (Address Offset + 0x2000, 0x2008 …)
TXE FIFO TB* DLC Register (Address Offset + 0x2004, 0x200C …)
CAN FD RX Message Space (Sequential/FIFO Buffers-RX FIFO-0) Register Descriptions
CAN FD RX Message Space (Sequential/FIFO Buffers-RX FIFO-1) Register Descriptions
RB*-ID Register (Address Offset + 0x2100, 0x2148 …0x4100, 0x4148 …)
RB*DLC Register (Address Offset + 0x2104, 0x214C …0x4104, 0x414C …)
RB*-DW0 Register (Address Offset + 0x2108, 0x2150…0x4108, 0x4150…)
RB*-DW1-15 Register (Address Offset + 0x210C, 0x2154…0x410C, 0x4154...)
Acceptance Filters
Acceptance Filtering when RX FIFO-1 is absent or disabled
Acceptance Filtering when RX FIFO-1 is enabled
AFMR* Register (Address Offset + 0x0A00, 0x0A08,…)
AFIR* Register (Address Offset + 0x0A04, 0x0A0C,…)
CAN FD RX Message Space (Mailbox Buffers) Register Descriptions
RB*-ID Register (Address Offset + 0x2100, 0x2148,…0x4100,...)
RB*-DLC Register (Address Offset + 0x2104, 0x214C,…0x4104,...)
RB*-DW Register (Address Offset + 0x2108, 0x210C,…0x2150, 0x2154, …0x4108,...)
MRB* Register (Address Offset + 0x2F00, 0x2F04,…)
Designing with the Core
Operating Modes and States
Configuration Mode
Normal Mode
(Internal) Loopback Mode
Sleep Mode
Snoop (Bus Monitoring) Mode
Protocol Exception State
Bus-Off Recovery State
Programming Model
Register Configuration Sequence
Message Transmission, Cancellation, and Reception
Transmission
Transmit Cancellation
Reception (Sequential Buffer/FIFO Mode)
Filtering when RX FIFO-1 is absent or disabled
Filtering when RX FIFO-1 is enabled
Reception (Mailbox Mode)
Clocking
Resets
System (Hard) Reset
Software Reset
Interrupts
Design Flow Steps
Customizing and Generating the Core
User Parameters
Output Generation
Constraining the Core
Required Constraints
Clock Frequencies
Simulation
Synthesis and Implementation
Example Design
Overview
Simulating the Example Design
Simulation Results
Example Sequence
Test Bench
Verification, Compliance, and Interoperability
Compliance Testing
Upgrading
Upgrading in the Vivado Design Suite
Port and Parameter Changes between v2.0 and v3.0
Parameter Changes between v1.0 and v2.0
Port Changes between v1.0 and v2.0
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
Interface Debug
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices