This section provides information about any changes to the user logic or port designations that take place when you upgrade to a more current version of this IP core in the Vivado Design Suite.
Parameter Changes
The following table shows the changes to parameters in the current version of the core.
| User Parameter Name | Display Name | New/Change/Removed | Details | Default Value |
|---|---|---|---|---|
| axisten_if_enable_rx_msg_intfc | Enable RX Message INTFC | New | When checked, messages are routed to the cfg_msg_received signal at the Receive Message Interface. Otherwise, they are routed to the CQ Interface. | False (not checked) |
| enable_auto_rxeq | Enable Auto RxEq | New | Selects Receiver Equalization in Auto Mode | False (not checked) |
| mcap_fpga_bitstream_version | MCAP Bitstream Version register value | New | Specify the value of the MCAP Bitstream Version register within the MCAP register space. | 00000000 |
Port Changes
The port in the following table appears when Shared logic option GT common in core is selected, and PLL type is not CPLL.
| Name | I/O | Width |
|---|---|---|
| ext_qpllxrcalenb | O | 1 Bit |
The ports in the following table appear when Shared logic option GT-Wizard in core is selected.
| Name | I/O | Width |
|---|---|---|
| ext_phy_clk_bufg_gt_ce | O | 1 Bit |
| ext_phy_clk_bufg_gt_reset | O | 1 Bit |
| ext_phy_clk_rst_idle | O | 1 Bit |
| ext_phy_clk_txoutclk | O | 1 Bit |
| ext_phy_clk_bufgtcemask | O | 1 Bit |
| ext_phy_clk_gt_bufgtrstmask | O | 1 Bit |
| ext_phy_clk_bufgtdiv | O | 8 Bits |
| ext_phy_clk_pclk2_gt | I | 1 Bit |
| ext_phy_clk_int_clock | I | 1 Bit |
| ext_phy_clk_pclk | I | 1 Bit |
| ext_phy_clk_phy_pclk2 | I | 1 Bit |
| ext_phy_clk_phy_coreclk | I | 1 Bit |
| ext_phy_clk_phy_userclk | I | 1 Bit |
| ext_phy_clk_phy_mcapclk | I | 1 Bit |
| ext_qpllxrcalenb | O | 1 Bit |