Spartan UltraScale+ Devices Available GT Quads - 1.3 English - PG213

The following table shows the PCIe® lane 0 GT Quad options available for the different AMD Spartan™ UltraScale+™ devices. The GT Quad location is shown using the GT Quad bank number rather than GT XY coordinates. The UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) provides a diagram describing the PCIe block locations relative to enabled GT Quads and includes both GT bank numbering and XY coordinates if needed.

The table lists the number of GT Quads available for selection per device, package and the PCIe block available. During IP customization, in the Basic Tab, select Advanced mode, select Enable GT Quad Selection, and make your GT quad selection.