A memory read request transfers across the completer request interface in the
same manner as a memory write request, except that the AXI4‑Stream packet
contains only the 16‑byte descriptor. The following timing diagrams show the transfer of
a memory read TLP received from the link across the completer request interface when the
interface width is configured as 64, 128, and 256 bits, respectively. The packet
occupies two consecutive beats on the 64-bit interface, while it is transferred in a
single beat on the 128- and 256-bit interfaces. The m_axis_cq_tvalid signal remains asserted over the duration of the packet.
You can prolong a beat at any time by deasserting m_axis_cq_tready. The sop signal in the m_axis_cq_tuser bus is asserted when the first descriptor byte is on the
bus.
The integrated block supplies the byte enable bits associated with the first
and last Dwords of the read request on the m_axis_cq_tuser sideband
bus. These bits are valid when the first descriptor byte transfers and are used to
determine the byte‑level starting address and the byte count associated with the
request. For the special cases of one-Dword and two-Dword reads, the byte enables can be
non-contiguous. The byte enables are contiguous in all other cases. A zero-length memory
read is sent on the CQ interface with the Dword count field in the descriptor set to 1
and the first and last byte enables set to 0.
The user application must respond to each memory read request with a Completion. A read request returns data as a single Completion or as multiple Split Completions. The integrated block sends these Completions through the Completer Completion (CC) interface. Completions for different requests can be sent in any order, while Split Completions for the same request are sent in order. The operation of the CC interface is described in Completer Completion Interface Operation.