Capabilities Tab - Capabilities Tab - v1.3 English - PG213

UltraScale+ Devices Integrated Block for PCI Express v1.3 Product Guide (PG213)

Document_ID
PG213
Release_Date
2026-07-31
Version
v1.3 English

The Capabilites settings are explained in this section as shown in the following figure.

Figure 1. Capabilities Tab
Total Physical Functions
Enables you to select the number of physical functions. The number of physical functions supported is 4.
PFx Max Payload Size
This field indicates the maximum payload size that the device or function can support for TLPs. This is the value advertised to the system in the Device Capabilities Register.
Extended Tag Field
This field indicates the maximum supported size of the Tag field. The options are:
  • When selected, 8-bit Tag field support (256 tags)
  • When deselected, 5-bit Tag field support (32 tags)
Enable Slot Clock Configuration
Enables the Slot Clock Configuration bit in the Link Status register.
  • When this option is selected, the link is synchronously clocked.
  • When this option is deselected, asynchronous clock in SRNS mode is supported. SRNS refers to a separate reference clock with No SSC (an asynchronous clock without SRIS support).