User Interface - User Interface - 4.0 English - PG211

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
Document ID
PG211
Release Date
2025-12-09
Version
4.0 English
Figure 1. Multiple Core with GT in Example Design Hierarchy

The GPIOs in the following table are provided to control the example design.

Table 1. User Input/Output Ports
Name Size I/O Description
sys_reset 1 I Reset for l_ethernet core.
gt_refclk_p 1 I Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
gt_refclk_n 1 I Differential input clk to GT. This clock frequency should be equal to the GT RefClk frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
dclk 1 I Stable/free running input clk to GT. This clock frequency should be equal to the GT DRP clock frequency mentioned in the Vivado IDE GT Selection and Configuration tab.
rx_gt_locked_led 1 O Indicates that GT has been locked.
rx_aligned_led 1 O Indicates RX aligned has been achieved.
completion_status

This signal represents the test status/result.

  • 5'd0: Test did not run.
  • 5'd1: PASSED 50GE/40GE CORE TEST SUCCESSFULLY COMPLETED
  • 5'd2: No block lock on any lanes.
  • 5'd3: Not all lanes achieved block lock.
  • 5'd4: Some lanes lost block lock after achieving block lock.
  • 5'd5: No lane sync on any lanes.
  • 5'd6: Not all lanes achieved sync.
  • 5'd7: Some lanes lost sync after achieving sync.
  • 5'd8: No alignment status or rx_status was achieved.
  • 5'd9: Loss of alignment status or rx_status after both were achieved.
  • 5'd10: TX timed out.
  • 5'd11: No tx data was sent.
  • 5'd12: Number of packets received did not equal the number of packets sent.
  • 5'd13: Total number of bytes received did not equal the total number of bytes sent.
  • 5'd14: An protocol error was detected.
  • 5'd15: Bit errors were detected in the received packets.
  • 5'd31: Test is stuck in reset.
restart_tx_rx_* 1 I This signal is used to restart the packet generation and reception for the data sanity test when the packet generator and the packet monitor are in idle state.
send_continuous_pkts_* 1 I

This port can be used to send continuous packets for board validation.

  • 1'b0 - Sends fixed 20 packets for simulation.
  • 1'b1 - Sends continuous packets for board.
mode_change_0 1 I This port is available only when Runtime Switchable is selected in Vivado IDE and this is used to switch the core speed.
core_speed_0 1 O This signal indicates the speed with which the core is working: 1’b1 = 40G and 1’b0 = 50G.