Statistics Counters - Statistics Counters - 4.0 English - PG211

The statistics counters provide histograms of the classification of traffic and error counts. These counters can be read either by a 1 on pm_tick or by writing a 1 to TICK_REG, depending on the value of MODE_REG[30](that is tick_reg_mode_sel).

The counters employ an internal accumulator. A write to the TICK_REG register causes the accumulated counts to be pushed to the readable STAT_*_MSB/LSB registers and simultaneously clear the accumulators. Next, the STAT_*_MSB/LSB registers can be read. In this way all values stored in the statistics counters represent a snapshot over the same time-interval.

The STAT_CYCLE_COUNT_MSB/LSB register contains a count of the number of RX core clock cycles between TICK_REG register writes. This allows for easy time-interval based statistics.

The counters have a default width of 48b. The counters saturate to 1s. The values in the counters are held until the next write to the TICK_REG register.

The first of the pair of addresses shown for the counters are the addresses of the LSB register, or bits 31:0 of the count. The MSB bits 47:32 of the counter are located at + 0x4 from the LSB.