Counters are 48 bits and require two 32-bit address spaces. The following tables provide the first address for each counter corresponding to the 32 LSBs and the next address contains the remaining 16 bits of MSBs in bits [15:0].The default value for all counters is 0.
Counters are cleared when read by tick_reg (or pm_tick
if so selected), but the register retains its value.
Each counter saturates at FFFFFFFFFFFF (hex).