Pause Interface - Control Ports - Pause Interface - Control Ports - 4.0 English - PG211

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
Document_ID
PG211
Release_Date
2025-12-09
Version
4.0 English
The following table describes the control signals.
Table 1. Pause Interface – Control Ports
Name I/O Clock Domain Description
ctl_rx_pause_enable[8:0] I rx_serdes_clk RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority.
Note: This signal only affects the RX user interface, not the pause processing logic.
ctl_tx_pause_enable[8:0] I clk TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets.