Normal Frame Reception - Normal Frame Reception - 4.0 English - PG211

The timing of a normal inbound frame transfer is represented below. The client must be prepared to accept data at any time as there is insufficient buffering within the core to allow for latency in the receive client. When frame reception begins, data is transferred on consecutive clock cycles to the receive client. During frame reception, rx_axis_tuser_tvalid is asserted to indicate that valid frame data is being transferred to the client on rx_axis_tdata. All bytes are always valid throughout the frame, as indicated by all rx_axis_tuser_mty bits being set to 0, except during the final transfer of the frame when rx_axis_tuser_eop is asserted. During this final transfer of data for a frame, rx_axis_tuser_mty bits indicate the final valid bytes of the frame.

The signals shown in the figure above waveform are described in the following subsections.

rx clk

The rx_clk_out signal should be used as the clock reference for all RX AXI4-Stream signals. All RX AXI signals are aligned to the rising edge of this clock.

rx_axis_tdata[127:0]

This bus provides the packet-oriented data corresponding to the received Ethernet frame. Data is clocked by therx_clk_out signal. The following figure illustrates how the end of an Ethernet frame is mapped onto the bit positions of the RX AXI4-Stream interface. Note the positions of the ENA0 and ENA1 signals relative to the bits positions of the RX AXI4-Stream bus. This mapping is for a 128-bit AXI4-Stream bus.

The following figure shows a normal receive cycle with back-to-back continuous transfers. A 124 byte packet starts on segment 0 and ends on segment 1. This is followed by a 99 byte packet that starts in the next clock cycle on segment 0 and ends on segment 0.

rx_axis_tuser_tvalid

When asserted, this signal indicates that data on the RX AXI bus is valid.

rx_axis_tuser_ena0, rx_axi_tuser_ena1

When asserted, this signal indicates that data for the associated segment is valid.

rx_axis_tuser_sop0, rx_axis_tuser_sop1

This signal indicates the start of an Ethernet frame on the RX AXI bus. There is one SOP signal for each segment.

rx_axis_tuser_eop0, rx_axis_tuser_eop1

This signal indicates the end of an Ethernet frame on the RX AXI bus. There is one EOP signal for each segment.

rx_axis_tuser_err0, rx_axis_tuser_err1

When this signal is asserted, it indicates that there is an error in the received frame. It is valid during the EOP cycle when ena and tvalid are asserted. There is one error signal for each segment.

The types of errors that can exist include:

• There was an FCS error
• The length was out of the valid range
• A bad 64B/66B code was received during receipt of the packet

rx_axis_tuser_mty0[2:0], rx_axis_tuser_mty1[2:0]

As in the TX AXI interface, the mty signal indicates how many bytes of the current cycle are unused (empty) during the last cycle of a received packet (the EOP cycle). There is one mty signal for each RX segment.