| 2:0 |
3'b000 |
RW |
gtwiz_loopback |
| 7:3 |
5'b00000 |
RW |
gtwiz_txprecursor |
| 12:8 |
5'b00000 |
RW |
gtwiz_txpostprecursor |
| 19:13 |
7'b0000000 |
RW |
gtwiz_txmainprecursor |
| 20 |
1'b0 |
RW |
gtwiz_rxcdrhold |
- The bit description mentioned (for
gtwiz_txprecursor, gtwiz_txpostcursor, gtwiz_txmaincursor,
gtwiz_rxcdrhold) is valid for non-GTM Versal devices only.
- For Versal GTM devices, valid bit description is: bits [8:3] for
gtwiz_txprecursor, [14:9] for gtwiz_txpostcursor, [21:15]
for gtwiz_txmaincursor and bit [22] of register is for
gtwiz_rxcdrhold.
- For more information, refer to
Versal
Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
|