- Designed to the Ethernet requirements for 50 Gb/s operation as defined in Schedule 3 of the 25G Ethernet Consortium (Ethernet Technology Consortium). See the note at the bottom of the page.
- Designed to the requirements for 40 Gb/s operation as defined in IEEE 802.3 Clause 82 IEEE Standard for Ethernet (IEEE Std 802.3-2015).
- Includes complete Ethernet MAC and PCS functions or standalone PCS.
- Simple packet-oriented user interface.
- Low latency mode.
- Comprehensive statistics gathering.
- Status signals for all major functional indicators.
- Delivered with a top-level wrapper including functional transceiver wrapper, IP netlist, sample test scripts, and AMD Vivado™ design tools compile scripts.
- Optional fee based AN/LT/KR Forward Error Correction (FEC) features.
- Optional KP4 FEC feature for GTM devices.
Note: To access the 25G
specification, visit the Ethernet Technology Consortium website.