This section describes the clocking for all the 40G/50G configurations at the component support wrapper layer. There are three fundamentally different clocking architectures depending on the functionality and options:
- PCS/PMA Only Clocking
- 40G/50G MAC with PCS/PMA Clocking
- Low Latency 40G/50G MAC with PCS/PMA Clocking
Also described is Auto-Negotiation and Link Training Clocking.
Note: When Data Path Interface is selected as the
256-bit Regular AXI4-Stream in the AMD Vivado™
IDE, the example design TX/RX
AXI4-Stream should use
tx_out_clk; otherwise this can lead to
packet mismatch.