MODE_REG: 0008 - 5.1 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2025-12-05
Version
5.1 English
Table 1. MODE_REG: 0008
Bits Default Type Signal
0 1 RW en_wr_slverr_indication
1 1 RW en_rd_slverr_indication
30 1 RW tick_reg_mode_sel
31 0 RW ctl_local_loopback 2
  1. The 0th and 1st bit of mode_reg register provides the flexibility to disable and enable the slv error. The user can write '0' to these bits to suppress the reporting of slv error.
  2. ctl_local_loopback is applicable for non-versal devices only.