For receive data, rx_axis_tdata[63:0], the port is logically
divided into lane 0 to lane 7. See the following table.
| Lane/rx_axis_tkeep | rx_axis_tdata[63:0] bits |
|---|---|
| 0 | 7:0 |
| 1 | 15:8 |
| 2 | 23:16 |
| 3 | 31:24 |
| 4 | 39:32 |
| 5 | 47:40 |
| 6 | 55:48 |
| 7 | 63:56 |
For receive data, rx_axis_tdata[63:0], the port is logically
divided into lane 0 to lane 7. See the following table.
| Lane/rx_axis_tkeep | rx_axis_tdata[63:0] bits |
|---|---|
| 0 | 7:0 |
| 1 | 15:8 |
| 2 | 23:16 |
| 3 | 31:24 |
| 4 | 39:32 |
| 5 | 47:40 |
| 6 | 55:48 |
| 7 | 63:56 |