| Bits | Default | Type | Signal |
|---|---|---|---|
| 0 | 0 | RW | ctl_tx_lat_adj_enb |
| 1 | 0 | RW | ctl_rx_lat_adj_enb |
| 2 | 0 | RW | ctl_tx_timstamp_adj_enb |
| 3 | 0 | RW | ctl_rx_timstamp_adj_enb |
| 4 | 0 | RW | ctl_core_speed |
| Bits | Default | Type | Signal |
|---|---|---|---|
| 0 | 0 | RW | ctl_tx_lat_adj_enb |
| 1 | 0 | RW | ctl_rx_lat_adj_enb |
| 2 | 0 | RW | ctl_tx_timstamp_adj_enb |
| 3 | 0 | RW | ctl_rx_timstamp_adj_enb |
| 4 | 0 | RW | ctl_core_speed |