Board Testing Steps for Auto-Negotiation and Link Training Using Versal GT Wizard Subsystem AXI4-Lite Interface - Board Testing Steps for Auto-Negotiation and Link Training Using Versal GT Wizard Subsystem AXI4-Lite Interface - 5.1 English - PG210

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2026-07-08
Version
5.1 English
  1. Perform the one-time uB and ANLT reset sequence to initialize the GT Wizard Subsystem microcontroller. After releasing sys_reset, wait 40 μs, then assert ubmbrst_0 to 1. After 1 μs, assert resetb_anlt_0 to 0. After another 1 μs, deassert resetb_anlt_0 to 1, then after 1 μs deassert ubmbrst_0 to 0.

    Keep reading gpo_0[15] until it reads 1, which indicates the GT Wizard Subsystem microcontroller has initialized and that the ANLT registers are ready for access. Wait an additional 110 μs before proceeding.

  2. Read the default values of the ANLT registers to verify the AXI4-Lite interface to the GT Wizard Subsystem is accessible. For example, read ANLT_LANE_ID_0 (0x157D0), ANLT_ABILITY_0 (0x157D8), ANLT_ADV_ABILITY_0 (0x157DC), ANLT_SETUP_0 (0x157D4), and ANLT_INTERRUPT_ENABLE_0 (0x157F8). Confirm the reads complete without AXI4-Lite errors.
  3. Write the ANLT_LANE_ID register to assign the lane identifier for the port. For example, write the value 0x00000001 to ANLT_LANE_ID_0 (0x157D0).
  4. Write the ANLT_ABILITY register to advertise the preferred FEC capability per IEEE 802.3 Clause 73. For 25GBASE-KR, write the value 0x00008000 to ANLT_ABILITY_0 (0x157D8). For 10GBASE-KR, write the value 0x00002100 to ANLT_ABILITY_0 (0x157D8).
  5. Write the ANLT_ADV_ABILITY register to advertise the preferred speed/protocol capability (extended technology ability field). For 25G, write the value 0x00000400 to ANLT_ADV_ABILITY_0 (0x157DC). For 10G, write the value 0x00000004 to ANLT_ADV_ABILITY_0 (0x157DC).
  6. Write 0x0000FFFF to ANLT_INTERRUPT_ENABLE_0 (0x157F8) to enable all ANLT interrupts.
  7. Write 0x00000070 to ANLT_SETUP_0 (0x157D4) to enable Auto-Negotiation and Link Training and start the negotiation sequence.
  8. Keep reading ANLT_STATUS_0 (0x157EC) until it reads 0x00000081, which indicates Auto-Negotiation is complete and the link status bit is set. After AN completes, read ANLT_RESULT_0 (0x157E4), ANLT_RESULT2_0 (0x157E8), and ANLT_LP_ADV_ABILITY_0 (0x157E0) to confirm the negotiated speed and the link partner's advertised abilities.
  9. Continue reading ANLT_STATUS_0 (0x157EC) until it reads 0x000X008F (where X is don't care; bits 16–15 can set in some cases, indicating LT frame lock but not impacting ANLT completion status), which indicates that Link Training is also complete and the datapath is ready to enter mission mode.
  10. After ANLT_STATUS_0 reads 0x000X008F, wait for rx_block_lock_led to assert High, confirming PCS RX block synchronization is achieved at the negotiated line rate.
  11. Monitor completion_status until it transitions from the initial value (5'h1F or 5'h00) to an active result. A value of 5'h01 indicates the traffic test passed. Any other non-zero value indicates a failure. For example, 5'h02 indicates no block lock on any lane and 5'h0F indicates bit errors were detected in the received packets.
Note: The addresses listed above apply to GTY/GTYP and GTM Lane 0. Use the corresponding addresses from the ANLT Register Addresses tables. For full bit-field definitions of all registers, refer to the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442) and Versal Auto Negotiation and Link Training Interface User Guide (UG1790) (registration required).