The following table shows the AXI4-Stream receive interface signals.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| rx_axis_tdata[63:0] | O | clk | AXI4-Stream Data to upper layer |
| rx_axis_tkeep[7:0] | O | clk | AXI4-Stream Data Control to upper layer |
| rx_axis_tlast | O | clk | AXI4-Streamsignal indicating an end of packet |
| rx_axis_tvalid | O | clk | AXI4-Stream Data Valid |
| rx_axis_tuser | O | clk |
AXI4-StreamUser Sideband interface 1 indicates a bad packet has been received 0 indicates a good packet has been received |
| rx_parityout[7:0] | O | clk | AXI4-Stream core-generated parity. Follows the same data lane mapping as rx_axis_tkeep. |