The Versal GT Wizard Subsystem IP contains the
ANLT registers and provides access to them through the AXI4-Lite
interface. The addresses differ between GTY/GTYP and GTM quad types. For full
bit-field definitions, refer to the
Versal Adaptive SoC Transceiver Subsystem Product
Guide (PG442).
Table 1. ANLT Register Addresses — GTY/GTYP Quad
| Register |
GTY/GTYP Lane 0 |
| ANLT_LANE_ID |
0x157D0 |
| ANLT_SETUP |
0x157D4 |
| ANLT_ABILITY |
0x157D8 |
| ANLT_ADV_ABILITY |
0x157DC |
| ANLT_LP_ADV_ABILITY |
0x157E0 |
| ANLT_RESULT |
0x157E4 |
| ANLT_RESULT2 |
0x157E8 |
| ANLT_STATUS |
0x157EC |
Table 2. ANLT Register Addresses — GTM Quad
| Register |
GTM Lane 0 |
| ANLT_LANE_ID |
0x14600 |
| ANLT_SETUP |
0x14604 |
| ANLT_ABILITY |
0x14608 |
| ANLT_ADV_ABILITY |
0x1460C |
| ANLT_LP_ADV_ABILITY |
0x14610 |
| ANLT_RESULT |
0x14614 |
| ANLT_RESULT2 |
0x14618 |
| ANLT_STATUS |
0x1461C |
| ANLT_INTERRUPT_ENABLE |
0x14628 |