The tx_serdes_refclk is the reference clock used to generate
the high-speed clock for the transmitting serial transceiver. This clock is used by the
Interlaken 600G IP core to source the data
going into each serial transceiver.
The frequency of the tx_serdes_refclk domains is calculated by
dividing the serial bit rate by the parallel bus width into each serial transceiver
block.
For example, if the serial bit rate is 25 Gb/s and the parallel bus is 128-bits
wide, the tx_serdes_refclk has a frequency of (25,000 Mb/s/128) =
195.3125 MHz.