Each Serializer/Deserializer (SerDes) macro can provide its own recovered clock
to the Interlaken 600G IP core. These clocks are
connected to the rx_serdes_clk[LANES-1:0] input pins and are used to
clock the per lane logic of each lane. It is possible to share the same clock among
multiple lanes. The core handles crossing these domains to the clk
domain.
The frequency of these domains is calculated by dividing the serial bit rate by the SerDes width for each serial transceiver block.
For example, if the serial bit rate is 25 Gb/s and the parallel bus is 128 bits
wide, the rx_serdes_clk[LANES-1:0] will have a frequency of (25,000
Mb/s/128) = 195.3125 MHz.