This directory contains the simulation register transfer level (RTL) files for both Interlaken 600G IP, the Out-of-band flow control modules, and a sample instantiation of the transceiver.
| Name | Description |
|---|---|
| {name}_interlaken_top.v | This is a REFERENCE top level file used to show the connectivity
between the {name}_interlaken_cores module and the
AMD transceiver. |
| {name}_interlaken_cores_int_bb.v | This is the clear text port list for the
{name}_interlaken_cores_int module. This file
can be used to instantiate
{name}_interlaken_cores_int. |
| cores.vp | This is the encrypted simulation model for the IP. |
| {name}_interlaken_cores.v | This is the clear text port list for the
{name}_interlaken_cores module. The port list
also has detailed descriptions for each port that can be used as a
quick reference guide. This module contains an instantiation of the
{name}_interlaken_cores_int module. |
| {name}_rx_oobfc*.v | These are the RX out-of-band flow control modules. The RTL is clear-text. |
| {name}_tx_oobfc*.v | These are the TX out-of-band flow control modules. The RTL is clear text. |
| {name}_TRANSCEIVER_WRAPPER.v | This file comprises a reference instantiation of the AMD transceiver that can be used with the Interlaken 600G IP core. This is meant only as a reference to help with integration. |
| {name}_syncer*.v | These clear text files are used by the out-of-band flow control
and interlaken_top modules. |