{name}/compile - {name}/compile - 1.2 English - PG209

Interlaken 600G LogiCORE IP Product Guide (PG209)
Document ID
PG209
Release Date
2025-08-29
Version
1.2 English

The compile directory contains the EDIF netlist along with sample scripts and constraints to implement the core.

Table 1. compile Directory
Name Description
{name}/compile/xilinx/interlaken_top/edif/rev_1/{name}_interlaken_cores.edf This is the EDIF netlist file that must be used during synthesis and implementation of the FPGA.
{name}/compile/xilinx/interlaken_top/vivado/*

This directory contains an XDC file with timing constraints for the core, a sample compile script that uses Vivado design tools to compile the provided IP/RTL and sample log files from the compilation.

Note: This directory is provided in the build when Vivado Design Suite is selected at the time of configuration.