Typical Operation - Typical Operation - 1.2 English - PG209

Interlaken 600G LogiCORE IP Product Guide (PG209)

Document ID
PG209
Release Date
2025-08-29
Version
1.2 English

The Interlaken 600G IP core is designed to be as flexible as possible and to be used in many different applications. As such, the core provides all of the flexibility offered by the Interlaken protocol. Flow control information is automatically extracted by the RX path of the Interlaken 600G IP core. You must monitor the flow control information and ensure proper data transmission through the Interlaken 600G IP core. Also, the core TX path consists of a single pipeline with a single memory buffer. You must build the scheduling mechanism external to the core to multiplex data from different logical channels.

Following are the steps after the Interlaken 600G IP core is powered up.

  1. After the device is powered up and the reset procedure completed, the core TX path starts transmitting Control/Idle words to align and synchronize the receiving device Interlaken interface. Similarly, the Interlaken 600G IP core RX path receives Control/Idle words and completes its own synchronization procedure.
  2. Set all of the flow control inputs to the Interlaken 600G IP core TX path to the XOFF state to prevent any real data transfer.
  3. The RX path is eventually aligned and synchronized and signals the user logic that synchronization is complete. You can then turn the flow control information from XOFF to XON for any of the channels that are ready to accept data.
  4. When the other device is ready to receive data, it sends XON information to the core. The core will signal the user logic which channels can be used for data transmission.

These steps provide a simple and easily implemented procedure for using theInterlaken 600G IP core. You build a scheduler to multiplex data among the different logical channels and use the flow control information output by the core to manage the scheduling function. Lower-level Interlaken protocol details do not affect the outcome of designs using this core.