TX LBUS Interface - TX LBUS Interface - 1.2 English - PG209

The synchronous TX Local bus interface accepts packet-oriented data of an arbitrary length. It accepts data in either Packet Mode or Burst-Interleaved Mode.

All signals are synchronous relative to the rising edge of the clk port.

The LBUS is very wide (1,024, 1,536 or 2,048-bit) and thus very few packets are likely to have sizes that are a multiple (or near multiple) of the LBUS width. Consequently, the LBUS is divided into 128-bit segments, with multiple transfers presented in parallel during the same clock cycle. This permits a (previous) packet to end and a (new) packet to begin in the same clock cycle. Each segment has a full complement of control signals. Use of segments allows the LBUS to be highly used and provides high throughput through the Interlaken 600G IP core.

The 128-bit segments are ordered 0 to 15 (for a 2,048-bit LBUS) or 0 to 11 (for a 1,536-bit LBUS or 0 to 7 (for a 1,024-bit LBUS). The first of the 128-bit transfers occurs on segment 0 (that is, tx_datain0), the second on segment 1 (that is, tx_datain1), and so forth.

Data is transferred on a given tx_datain<N> segment when the corresponding tx_enain<N> is asserted. The TX core logic stores incoming data and does not forward it until it has sufficient quantity for a complete burst. Consequently, it is acceptable to have clock cycles in which none of the tx_enain<N> signals are active. However, in any cycle where any tx_enain<N> is asserted, it is required for tx_enain0 to be asserted. Furthermore, segments must be filled in sequence with no gaps between active segments.

In other words, if tx_enain<i> is set to 1, then tx_enain<i-1> must also be set to 1, for i ranging from 1 to 15 (for a 2,048-bit bus) or 1 to 11 (for a 1,536-bit bus) or 1 to 7 (for a 1024-bit bus).

The start of a packet is identified by the assertion of tx_sopin<N> with the corresponding tx_enain<N>. Similarly, the end of a packet is identified by the assertion of tx_eopin<N> with the corresponding tx_enain<N>. Both tx_sopin<N> and tx_eopin<N> can be asserted on a given cycle. This occurs for packets that are less than or equal to the LBUS width. Furthermore, both tx_sopin<N> and tx_eopin<N> can be asserted for a given segment on a given cycle. This occurs for packets that are less than or equal to 16 bytes (the segment size).

The channel number for a packet is presented on the tx_chanin<N> input of the corresponding segment and must be valid for every segment where tx_enain<N> is asserted. After SOP has been asserted for a certain channel number, it cannot be asserted again with that channel number until EOP has been asserted for the same channel number.

The first 16 bytes of a packet must be presented on a given tx_datain<N> segment during the cycle that the corresponding tx_sopin<N> and tx_enain<N> are asserted. In other words, the SOP is segment aligned. Subsequent 16-byte chunks of data are transferred during segments that follow. For each of those segments, the corresponding tx_sopin<N> must be negated. The first byte of the packet is written on bits [127:120] of the segment, the second byte on bits [119:112], and so forth.

The last bytes of the packet are transferred on the tx_datain<N> segment whose corresponding tx_eopin<N> is asserted. Unless tx_eopin<N> is asserted, all 16 bytes of tx_datain<N> must contain valid data whenever tx_enain<N> is asserted. Note that if Burst-Interleaved Mode is employed, then segments containing data from other packets can be interleaved with segments containing data for a given packet. The tx_chanin<N> identifies the packets from different channels.

During the segment containing the last bytes of a packet, the tx_mtyin<N> port reflects how many bytes of the corresponding tx_datain<N> are invalid (or empty). A given tx_mtyin<N> port only has meaning during cycles when both the corresponding tx_enain<N> and tx_eopin<N> are asserted. If tx_mtyin<N> has a value of 0x0, there are no empty byte lanes (that is, all bits of the segment are valid).

If tx_mtyin<N> has a value of 0x1, then one byte lane is empty, specifically tx_datain<N>[7:0] does not contain valid data. If tx_mtyin<N> has a value of 0x2, then two byte lanes are empty — specifically tx_datain<N>[15:0] does not contain valid data. If tx_mtyin<N> has a value of 0x3, then three byte lanes are empty — specifically tx_datain<N>[23:0] does not contain valid data. And so forth for other possible values of tx_mtyin<N>.

During the segment containing the last bytes of a packet, when tx_eopin<N> is asserted with tx_enain<N>, the corresponding tx_errin<N> can also be asserted. This marks the packet as being in error and this information is included in the final Interlaken Control Word associated with this packet. When tx_eopin<N> and tx_errin<N> are sampled as 1, the value of tx_mtyin<N>[2:0] is ignored and treated as equal to 000, while tx_mtyin<N>[3] is used as usual.

Optimal use of the Interlaken bandwidth requires data on the TX Local bus to be written at a rate faster than can be delivered on the Interlaken serial interface. This means that there must be back-pressure, or flow-control, on the TX LBUS. The signals used to implement back-pressure are tx_rdyout, tx_ovfout, and ctl_tx_rdyout_thresh.

These signals are common for all segments. Data can be safely written (one or more tx_enain<N> might be asserted) whenever tx_rdyout is asserted. After tx_rdyout is negated, additional writes, using tx_enain<N>, can be safely performed provided tx_ovfout is never asserted. When responding to back-pressure during a clock cycle, none of the tx_enain<N> can be active. When tx_rdyout is asserted again, additional data can be written. If the back-pressure mechanism is violated, tx_ovfout is asserted to indicate the violation.

The number of additional writes that can be performed after tx_rdyout is negated is determined by the signal tx_rdyout_thresh. If tx_ovfout is ever asserted, the TX core must be reset before resuming normal operation.

See Transmitter FIFO Threshold for more information on setting ctl_tx_rdyout_thresh.