When bringing up a board for the first time and the Interlaken IP core does not seem to be achieving lane alignment, the most likely problem is related to signal integrity. Signal integrity issues must be addressed before any other debugging can take place.
Even if lane alignment is achieved, if there are periodic CRC32 errors, then signal
integrity issues are indicated. Check the crc32_err signals to
assist with debug.
Signal integrity should be debugged independently from the Interlaken IP core. The
following procedures should be carried out.
Note: It is assumed that the PCB itself has been designed and manufactured in
accordance with the required trace impedances and trace lengths.
- Transceiver Settings
- Checking For Noise
- Bit Error Rate Testing
If assistance is required for transceiver and signal integrity debugging, contact AMD technical support.