The Interlaken 600G IP core example design is shown in following figure.
Figure 1. Example Design
The example design consists of the following:
- The Interlaken 600G IP core netlist
- A reference serial transceiver (GT) wrapper
- An example top-level illustrating the connection between the Interlaken 600G IP core and the GTs
- A demonstration test bench to exercise the example design
- An example simulation and compile scripts
The Interlaken 600G IP core example design is tested with Questa Advanced Simulator, Cadence Incisive Enterprise Simulator (NC-Verilog) and Synopsys VCS. For the supported version of the AMD tools, see the README file provided with the Interlaken 600G IP core release.