Table 1 and Table 2 show the port list of the TX_OOBFC and RX_OOBFC modules along with a description of each pin respectively.
The LANES parameter is equal to the number of SerDes lanes. The MAX_CALLEN parameter
is set to the maximum number of calendar entries supported by the core from 32 to
256.
| Name | Direction | Domain | Description |
|---|---|---|---|
| Clocking and Resets | |||
| clk | I | All signals between the TX_OOBFC and the user
logic are synchronized to the positive edge of clk.
In typical applications, this clock should be tied to the same clock
that is used to run the user-side interface of the Interlaken 600G IP core. |
|
| clk_tx_ref | I | This clock is used to generate the flow control signals. You are required to supply a clock with a maximum frequency of 200 MHz. The 200 MHz limitation (which is twice the OOBFC clock) is defined by the Interlaken Protocol Definition, Revision 1.2 | |
| reset | I | async | Active-High, asynchronous reset input. This signal is
automatically synchronized to the appropriate clock domain by the
TX_OOBFC. All circuits in the module are reset
while this input has a value of 1. This signal must remain asserted
until after several clock cycles on both the clk
and clk_tx_ref inputs. |
| User-Side Interface – TX_OOBFC Signals | |||
| tx_fc[MAX_CALLEN-1:0] | I | clk | Input data bus containing the flow control information to be
transmitted by the TX_OOBFC. The width of the bus
is set by the MAX_CALLEN parameter. Unused bits, as defined by
tx_callen_minus1[7:0], must be tied to 0.
Interlaken defines a value of 1 as XON for the corresponding
channel, and a value of 0 as XOFF for the corresponding
channel. |
| tx_callen_minus1[7:0] | I | clk | This input sets the calendar length for flow control information for
the TX_OOBFC. Allowed values are 0
to MAX_CALLEN-1. For example, when MAX_CALLEN is set to 32, tx_callen_minus1[7:0] can be set to
any value between 0 and 31. It is up to you to ensure that this
input is set correctly. Incorrect setting results in undetermined
behavior. This input should only be changed when reset is asserted
(that is, set to 1). Changing the value on this input when not in
reset can result in incorrectly transmitted flow-control or status
information. |
| tx_lanes_minus1[LANES_LOG2-1:0] | I | clk | This input sets the number of lanes to be included in the Status Message. Allowed values are 0 to LANES-1. This value should be set to the number of lanes (minus 1) expected by the receiver. An incorrect setting can result in undetermined behavior. This input should only be changed when reset is asserted (that is, set to 1). |
| tx_intf_status | I | clk | Indicates the health of the interface to be transmitted to the other device as described in the Interlaken specification. A value of 1 indicates the interface is healthy. If unused, this input should be a set to a value of 1. |
| tx_lane_status[LANES-1:0] | I | clk | Indicates the health of each lane to be transmitted to the other device as described in the Interlaken specification. A value of 1 indicates the corresponding lane is healthy. Bit 0 corresponds to lane 0, bit 1 corresponds to lane 1, and so on. If unused, all inputs should be a set to a value of 1. |
| tx_update[3|2|1|0:0] | O | clk | This output bus indicates when the status and flow control
information are latched for transmission. If
tx_update[0] is asserted,
tx_fc[63:0], tx_lane_status,
and tx_intf_status bits will be latched at the
completion of the current clock cycle; if
tx_update[1] is asserted,
tx_fc[127:64] will be latched at the end of the
current clock cycle; if tx_update[2] is asserted,
tx_fc[191:128] will be latched at the end of
the current clock cycle and so on. |
| tx_status_enable | I | clk | This input can be used to enable and disable the transmission of
the interface and lane status. When this input is a value of 1,
tx_intf_status and
tx_lane_status operate according to the
descriptions. When this input is a value of 0, the values on
tx_intf_status and
tx_lane_status are ignored and the interface
and lane status are not transmitted. If the transmission of the
interface and lane status are not required, this value should be
tied to a value of 0. |
| tx_err | O | clk | If the clock rates are incorrect for the selected calendar
length, the signal tx_err can be asserted to notify
you of this configuration error. |
| Device Interface – TX_OOBFC Signals 1 | |||
| TX_FC_CLK (LVCMOS) | O (LVCMOS) | This is the source synchronous clock generated by
TX_OOBFC as defined by the Interlaken protocol.
The frequency of this clock is one-half the frequency of
clk_tx_ref. For example, if
clk_tx_ref is 200 MHz, this clock is 100 MHz.
This signal must be connected directly to a device output
pin. |
|
| TX_FC_DATA | O (LVCMOS) | The flow control information is transmitted by the
TX_OOBFC with this signal as defined by the
Interlaken protocol. This signal must be connected directly to a
device output pin. |
|
| TX_FC_SYNC | O (LVCMOS) | This signal is used to synchronize the transmitted flow control information as defined by the Interlaken protocol. This signal must be connected directly to a device output pin. | |
|
|||
| Name | Direction | Domain | Description |
|---|---|---|---|
| Clocking and Resets | |||
| clk | I | All signals between the RX_OOBFC and the user
logic are synchronized to the positive edge of clk. In typical
applications, this clock should be tied to the same clock used to
run the user-side interface of the Interlaken 600G IP core. In order for correct
operation in the RX_OOBFC, the frequency of this
clock must be at least 33% faster than the frequency of
RX_FC_CLK. For example, if the frequency of
RX_FC_CLK is 100 MHz, the frequency of clk must
be at least 133 MHz. |
|
| reset | I | async | Active-High, asynchronous reset input. This signal is
automatically synchronized to the appropriate clock domain by the
RX_OOBFC. All circuits in the module are reset
while this input is a value of 1. This signal must remain asserted
until after several clock cycles on both the clk and
RX_FC_CLK inputs. |
| User-Side Interface – RX_OOBFC Signals | |||
| rx_fc[MAX_CALLEN-1:0] | O | clk |
Output data bus to the user logic containing the flow control
information received by the If the calendar length for the received flow control information has less than MAX_CALLEN entries, the unused bits are undefined and should be ignored. It is up to you to monitor this bus and take appropriate action as flow control information is changed. When an unhealthy interface status is received, as indicated by
When a CRC error is detected, the outputs |
| rx_crcerr | O | clk | Indicates if an error was observed in the CRC field of the
incoming status or flow control information. A value of 1 indicates
a CRC error was detected. When this bit is a value of 1, the outputs
rx_fc, rx_intf_status, and
rx_lane_status are not updated and can be
ignored. The cause of a CRC error can be due to clk
not being sufficiently faster than RX_FC_CLK as
required for correct operation. |
| rx_overflow | O | clk | Indicates that clk is not faster
than RX_FC_CLK as required for
correct operation. |
| rx_intf_status | O | clk | Indicates the health of the receive interface as described in the
Interlaken specification. When this output has a value of 0, all
flow-control bits in the rx_fc bus will be XOFF
(that is, 0). |
| rx_lane_status[LANES-1:0] | O | clk | Indicates the health of the corresponding receive lanes as
described in the Interlaken specification. Bit 0 corresponds to lane
0, bit 1 corresponds to lane 1, and so on. When any bit of this bus
has a value of 0, all flow-control bits in the
rx_fc bus will be XOFF (that is, 0). |
| rx_update [3|2|1|0:0] | O | clk | Indicates a valid CRC4 was detected and rx_fc
bits were updated. If rx_update[0] is asserted, the
CRC4 associated with rx_fc[63:0] was valid and
rx_fc[63:0] were updated; if
rx_update[1] is asserted, the CRC4 associated
with rx_fc[127:64] was valid and
rx_fc[127:64] were updated, and so on. |
| rx_callen_minus1[7:0] | O | clk | Indicates the length of the most recently received calendar. |
| rx_force_xoff_if_crcerr | I | clk | When this input is a value of 1, all bits of
rx_fc are forced to XOFF if an CRC error is
detected. |
| Device Interface – RX_OOBFC Signals 1 | |||
| TX_FC_CLK | I(LVCMOS) |
This the source-synchronous clock used by
This signal must be connected directly to a device input pin. |
|
| RX_FC_DATA | I (LVCMOS) |
The flow control information is received by the
This signal must be connected directly to a device input pin. |
|
| RX_FC_SYNC | I (LVCMOS) | This signal is used to synchronize the transmitted flow control information as defined by the Interlaken protocol. This signal must be connected directly to a device output pin. | |
|
|||