Port Descriptions - Port Descriptions - 1.2 English

The following table shows the port list for the Interlaken IP core. More detail on the use of each signal is given in User Side Interface. The variable LANES represents the number of high-speed serial transceiver lanes used in the core, and the SERDES_WIDTH variable represents the width of the parallel bus to/from the serial transceiver macros. The variable LBUS_WIDTH represents the width of the parallel bus to/from the user logic. The variable N represents the segment number.

Important: Static signals are control signals that can be changed only when the corresponding reset is asserted. Their values must be held static during the normal operation of the core.

Table 1. Port List
Name	Direction	Domain	Description
Transceiver I/O
rx_serdes_data[SERDES_WIDTH-1:0]	I	rx_serdes_clk	Data bus from the serial transceiver macros. There are LANES `rx_serdes_data` buses; one bus for each serial transceiver lane and each bus has SERDES_WIDTH bits. By definition, bit [SERDES_WIDTH-1] is the first bit received by the Interlaken 600G IP core. Bit [0] is the last bit received. The core supports an even width serial transceiver bus. The minimum supported width is 64 bits. Typical widths are 64 and 128. When the 64/67 transceiver gearbox is used, additional signals will be present to indicate the data sequence. Refer to the appropriate transceiver guide.
tx_serdes_data[SERDES_WIDTH-1:0]	O	tx_serdes_refclk	Data bus to the serial transceiver macros. There are LANES`tx_serdes_data` buses; one bus for each serial transceiver lane and each bus has SERDES_WIDTH bits. By definition, bit [SERDES_WIDTH-1] is the first bit transmitted by the Interlaken 600G IP core. Bit [0] is the last bit transmitted. The core supports an even width serial transceiver bus. The minimum supported width is 64 bits. Typical widths are 64 and 128. When the 64/67 transceiver gearbox is used, additional signals will be present to indicate the data sequence. Refer to the appropriate transceiver guide.
rx_serdes_clk[LANES-1:0]	I		Recovered clock of each serial transceiver lane. The `rx_serdes_data` bus for each lane is synchronized to the positive edge of the corresponding bit of this bus.
rx_serdes_reset[LANES-1:0]	I	async	Asynchronous Reset for each RX serial transceiver lane. The recovered clock for each serial transceiver lane has associated with it an active-High reset. This signal should be asserted whenever the associated recovered clock is not operating at the correct frequency. The core handles synchronizing each `rx_serdes_reset` signal to the appropriate clock domain. Generally, this signal is connected to a Phase-Locked Loop (PLL) lock signal.
tx_serdes_refclk	I		Reference clock for the TX lanes datapath. This clock must be connected to the same reference clock used to drive the TX serial transceivers. The `tx_serdes_data` bus for each lane is synchronized to the positive edge of the this clock.
tx_serdes_refclk_reset	I	async	Asynchronous Reset for TX Reference clock. This active-High signal should be asserted whenever the `tx_serdes_refclk` input is not operating at the correct frequency. The core handles synchronizing the `tx_serdes_refclk_reset` signal to the appropriate clock domain.
LBUS Interface – Clock/Reset Signals
clk	I		Local bus clock. All signals between the core and the user side logic are synchronized to the positive edge of this signal.
rx_reset	I	async	Asynchronous reset for the RX circuits. This signal is active-High (1= reset) and must be held High until all of the clocks for the RX path are fully active. The core handles synchronizing the `rx_reset` input to the appropriate clock domains.
tx_reset	I	async	Asynchronous reset for the TX circuits. This signal is active-High (1= reset) and must be held High until all of the clocks for the TX path are fully active. The core handles synchronizing the `tx_reset` input to the appropriate clock domains within the Interlaken 600G IP core.
LBUS Interface – RX Path Signals
rx_dataout<N>[127:0]	O	clk	Receive Data for LBUS segment <N>. This port is only valid in cycles in which the corresponding `rx_enaout<N>` is sampled as 1. The overall LBUS consists of LBUS_WIDTH/128 of these segments. The segments are ordered 0 to (LBUS_WIDTH/128)-1. For example, a 2,048-bit LBUS will have receive data ports from rx_dataout0 to rx_dataout15. The overall ordering of data transfer is such that the first of the 128-bit transfers occurs on segment 0, the second on segment 1, and so forth.
rx_chanout<N>[7:0]	O	clk	Receive Channel Number for LBUS segment <N>. This port indicates the channel number of the data that is present on the corresponding `rx_dataout<N>` segment. This port is only valid in cycles in which the corresponding `rx_enaout<N>` is sampled as 1. When the channel extension feature has been implemented, this bus will be wider.
rx_enaout<N>	O	clk	Receive LBUS Enable for LBUS segment <N>. This signal qualifies the other signals of the corresponding segment <N> of the RX LBUS interface. Signals of the corresponding segment are only valid in cycles in which `rx_enaout<N>` is sampled as a 1.
rx_sopout<N>	O	clk	Receive start of packet (SOP) for LBUS segment <N>. When this signal is sampled as a 1, it indicates that the SOP is present on the corresponding `rx_dataout<N>` segment. This signal is only valid in cycles in which the corresponding `rx_enaout<N>` is sampled as a 1.
rx_eopout<N>	O	clk	Receive end of packet (EOP) for LBUS segment <N>. When this signal is sampled as a 1, it indicates that the EOP is present on the corresponding `rx_dataout<N>` segment. This signal is only valid in cycles in which the corresponding `rx_enaout<N>` is sampled as a 1.
rx_errout<N>	O	clk	Receive Error for LBUS segment <N>. When this signal is sampled as a 1, it indicates an error in the packet whose data is present on the corresponding `rx_dataout<N>` segment. This signal is only valid in cycles when both the corresponding `rx_enaout<N>` and `rx_eopout<N>` are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet whose data is present on the corresponding `rx_dataout<N>` segment.
rx_mtyout<N>[3:0]	O	clk	Receive Empty for LBUS segment <N>. This port indicates how many bytes are empty or invalid on the corresponding `rx_dataout<N>` segment. It is only valid for the segment that contains the last data for a given packet. In other words, this port is only valid in cycles when both the corresponding `rx_enaout<N>` and `rx_eopout<N>` are sampled as 1. When `rx_errout<N>` and `rx_enaout<N>` are sampled as 1, the value of `rx_mtyout<N>[2:0]` is always 000, while `rx_mtyout<N>[3]` is set as usual.
LBUS Interface – TX Path Signals
tx_rdyout	O	clk	Transmit LBUS Ready. This signal indicates whether the Interlaken 600G IP core TX path is ready to accept data and provides back-pressure to the user logic. A value of 1 means the user logic can pass data to the Interlaken 600G IP core. A value of 0 means the user logic must stop transferring data to the Interlaken 600G IP core. The exact timing for the assertion of `tx_rdyout` depends on the value of `ctl_tx_rdyout_thresh[2:0]`.
tx_ovfout	O	clk	Transmit LBUS Overflow. This signal indicates whether you have violated the back-pressure mechanism provided by the `tx_rdyout` signal. If `tx_ovfout` is sampled as a 1, a violation has occurred. Design the rest of the user logic to prevent an overflow of the TX interface. If an overflow does occur, and the root cause is known, a reset is required on the TX core to resume operation.
tx_datain<N>[127:0]	I	clk	Transmit Data for LBUS segment<N>. This port contains data from the user logic. This port is only sampled in cycles in which the corresponding `tx_enain<N>` is sampled as a 1. The overall LBUS consists of LBUS_WIDTH/ 128 of these segments. The segments are ordered 0 to (LBUS_WIDTH/128)-1. For example, a 2,048-bit LBUS will have transmit data ports from `tx_datain0` to `tx_datain15`. The overall ordering of data transfer is such that the first of the 128-bit transfers occurs on segment 0, the second on segment 1, and so forth.
tx_chanin<N>[7:0]	I	clk	Transmit Channel Number for LBUS segment<N>. This port indicates the channel number of the data that is present on the corresponding `tx_datain<N>` segment. This port is only sampled in cycles in which the corresponding `tx_enain<N>` is sampled as 1. When the channel extension feature is implemented, this bus will be wider as required.
tx_enain<N>	I	clk	Transmit Enable for LBUS segment<N>. This signal qualifies the other signals of the corresponding segment <N> of the TX LBUS Interface. Signals of the corresponding segment are only valid in cycles in which `tx_enain<N>` is sampled as a 1.
tx_sopin<N>	I	clk	Transmit Start-Of-Packet for LBUS segment<N>. When this signal is sampled as a 1, it indicates that the start-of-packet (SOP) is present on the corresponding `tx_datain<N>` segment. This signal is only valid in cycles in which the corresponding `tx_enain<N>` is sampled as a 1.
tx_eopin<N>	I	clk	Transmit EOP for LBUS segment<N>. When this signal is sampled as a 1, it indicates that the EOP is present on the corresponding `tx_datain<N>` segment. This signal is only valid in cycles in which the corresponding `tx_enain<N>` is sampled as a 1.
tx_errin<N>	I	clk	Transmit Error for LBUS segment<N>. When this signal is sampled as a 1, it indicates an error in the packet whose data is present on the corresponding `tx_datain<N>` segment. This signal is only valid in cycles when both the corresponding `tx_enain<N>` and `tx_eopin<N>` are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet whose data is present on the corresponding `tx_datain<N>` segment.
tx_mtyin<N>[3:0]	I	clk	Transmit Empty for LBUS segment<N>. This port indicates how many bytes are empty or invalid on the corresponding `tx_datain<N>` segment. It is only valid for the segment that contains the last data for a given packet. In other words, this port is only valid in cycles when both the corresponding `tx_enain<N>` and `tx_eopin<N>` are sampled as 1. When `tx_errin<N>` and `tx_enain<N>` are sampled as 1, the value of `tx_mtyin<N>[2:0]` is ignored and treated as if it was 000, while `tx_mtyin<N>[3]` is used as usual.
tx_bctlin<N>	I	clk	Transmit force insertion of Burst Control word at LBUS segment<N>. This port is used to force the insertion of a Burst Control Word into the outbound data stream. When `tx_bctlin<N>` and `tx_enain<N>` are sampled as a 1, a Burst Control Word is inserted before the data on `tx_datain<N>` is transmitted, even if no Burst Control Word is required. This port is used by an external scheduler to reduce the bandwidth lost in the process of complying with the Interlaken BurstShort parameter (see Use of tx_bctlin in Chapter 3.) Use of this input is not a requirement for correct Interlaken 600G IP core operation. If this input is unused, it should be tied to 0.
LBUS Interface – TX Path Control/Status Signals
ctl_tx_enable	I	clk	TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only Idle Control Words (and the Meta Frame Words) are transmitted by the Interlaken 600G IP core. This input should not be set to 1 until the peer receiver (that is, the receiver in the other device) is fully aligned and ready to receive data. Otherwise, loss of data can occur. This input can be used for link-level flow control. For example, setting this input to 0 halts transmission of data and results in the entire link going into XOFF state.
ctl_tx_fc_stat[MAX_CALLEN-1:0]	I	clk	TX In-Band Flow Control Input. These signals are used to set the status for each calendar position in the inband-flow control mechanism (see the Interlaken Protocol specification). A value of 1 means XON, a value of 0 means XOFF. These bits are transmitted in the Interlaken Control Word bits [55:40]. Note: MAX_CALLEN refers to the maximum number of calendar entries and is selected at the time of configuration.
ctl_tx_fc_callen[3:0]	I	static	TX Flow Control Calendar Length Input. This input controls the number of bits of `ctl_tx_fc_stat` that are actually used. The settings for calendar length are as follows: 0x0 = 16 entries 0x1 = 32 entries 0x3 = 64 entries 0x7 = 128 entries 0xF = 256 entries All other values are reserved and must not be used. This input should only be changed when `tx_reset` is asserted. Additional values are possible if the channel extension feature is implemented. This bus will be wider as required when MAX_CALLEN exceeds 256.
ctl_tx_mubits[7:0]	I	clk	TX Multiple-Use Control Bits. This port contains the 'Multi-Use' field of the Interlaken Control Word (see Interlaken Protocol specification). The value of the port is transmitted in the Interlaken Control Word bits[31:24]. You must define the function of this port. If the port is not used, all bits must be set to 0.
ctl_tx_rlim_enable	I	clk	TX Rate Limiter Enable. This signal is used to enable the Rate Limiter. A value of 1 turns on the Rate Limiter and a value of 0 turns off the Rate Limiter.
ctl_tx_rlim_max[11:0]	I	static	TX Rate Limiter Maximum Token Count. This port is used to set the maximum number of tokens in the bucket. A token is equal to 1 byte.
ctl_tx_rlim_delta[11:0]	I	static	TX Rate Limiter Delta. This port is used to set the number of tokens to add to the bucket each interval. A token is equal to 1 byte.
ctl_tx_rlim_intv[7:0]	I	static	TX Rate Limiter Update Interval. This port is used to set the number of Local bus clock cycles between additions of `ctl_tx_rlim_delta` tokens to the bucket.
ctl_tx_burstmax[1:0]	I	static	Interlaken TX BurstMax. This port sets the BurstMax parameter for the TX as follows: 0x0 = 64 bytes 0x1 = 128 bytes 0x2 = 192 bytes 0x3 = 256 bytes Note: Some configurations support only 256 bytes. All other port settings are reserved and must not be used
ctl_tx_burstshort[2:0]	I	static	Interlaken TX BurstShort. This port sets the BurstShort parameter for the TX as follows: 0x1 = 64 bytes 0x3 = 128 bytes 0x5 = 192 bytes 0x7 = 256 bytes All other values are reserved and must not be used. Some configurations support only 64 bytes.
ctl_tx_diagword_lanestat[LANES-1:0]	I	async	Lane Status messaging inputs. This port sets bit 33 in the Diagnostic Word for the respective lane. See Interlaken Protocol Definition, Revision 1.2
ctl_tx_diagword_intfstat	I	async	Interface Status Message input. This signal sets bit 32 in the Diagnostic Word of each lane. See Interlaken Protocol Definition, Revision 1.2
ctl_tx_rdyout_thresh[2:0]	I	clk	Threshold value for the First In First Out (FIFO) in the TX path.
ctl_tx_disable_skipword	I	static	Skip Word Injection Deletion. As required by the Interlaken specification, a skip word is inserted once per Meta Frame to permit clock compensation through a repeater function. If the Interlaken 600G IP core is not transmitting through an intermediary device, but is simply transmitting to an "ultimate" receiver such as another Interlaken 600G IP core, this input can be set to a value of 1. See Section 5.4.7 of the Interlaken specification revision 1.2. This input should only be changed when `tx_reset` is asserted. Note: In some configurations, this feature is unsupported.
ctl_tx_mframelen_minus1[15:0]	I	static	TX Meta Frame Length minus one. This port sets the MetaFrameLength parameter for the TX and should be set to the desired length minus 1. For example, to set the MetaFrame length to 2,048, set this port to 2,047. The units of Metaframe length are Interlaken words. Each Interlaken word is 8 bytes (64 bits). This input should only be changed when `tx_reset` is asserted. Note: Some configurations require the MetaFrame length to be an even number.
stat_tx_underflow_err	O	clk	TX Underflow. This signal indicates if the LBUS interface is being clocked too slowly to properly fill the link with data. In normal operation, this signal is always sampled as 0. If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
stat_tx_overflow_err	O	clk	TX Overflow. This output should never be asserted and indicates a critical failure. In this case, a reset of the core is required.
stat_tx_burst_err	O	clk	TX Burst Error. This signal indicates that the TX LBUS rules have been violated. Consequently, a burst (that is, a sequence of Data Words between two Control Words) that violates the currently configured BurstShort can be sent to the TX Interlaken. When `stat_tx_burst_err` has been asserted, the TX core must be reset.
LBUS Interface – RX Path Control/Status Signals
ctl_rx_force_resync	I	async	RX Force `Resync` Input. This signal is used to force the RX lane logic to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation. Note: This input should normally be Low and should only be pulsed (1 cycle minimum pulse) to force realignment.
ctl_rx_packet_mode	I	async	RX Packet Mode Error Handling. This signal changes the way the error handler in the RX path processes errors. When this input is a value of 0, it assumes packets are arriving interleaved as segments (Burst-Interleaved Mode). When this input is a value of 1, it assumes packets are arriving as complete packets (Packet Mode). Use of this input ensures that packets delivered to the Local bus have the appropriate SOP and EOP pairing. This signal is not present when the Interlaken 600G IP core has been configured for packet mode operation only.
ctl_rx_burstmax[1:0]	I	static	Interlaken RX BurstMax. This port sets the BurstMax parameter for the RX as follows: 0x3 = 256 bytes All other values are reserved and must not be used. These inputs are only used with `stat_rx_burstmax_err`.
ctl_rx_mframelen_minus1[15:0]	I	static	RX Meta Frame Length minus one. This port sets the MetaFrameLength parameter for the RX and should be set to the desired length minus 1. For example, to set the MetaFrame length to 2,048, set this port to 2,047. The units of Metaframe length are Interlaken words. Each Interlaken word is 8 bytes (64 bits). This input should only be changed when `rx_reset` or `ctl_rx_force_resync` are asserted. Note: Some configurations require the MetaFrame length to be an even number.
stat_rx_burstmax_err	O	clk	RX BurstMax Error. When this signal is a value of 1, a burst (that is, a sequence of Data Words between two Control Words) was detected that was longer than the value of BurstMax specified by `ctl_rx_burstmax`. This signal is informational only and can be optionally ignored.
stat_rx_diagword_lanestat[LANES-1:0]	O	clk	Lane Status messaging outputs. This port reflects the most recent value in bit 33 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in `stat_rx_crc32_valid` is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2
stat_rx_diagword_intfstat[LANES-1:0]	O	clk	Lane Status messaging outputs. This port reflects the most recent value in bit 32 of the Diagnostic Word received on the respective lane. These bits should only be considered valid if the respective bit in `stat_rx_crc32_valid` is a value of 1. See Appendix A in the Interlaken Protocol Definition, Revision 1.2
stat_rx_crc32_valid[LANES-1:0]	O	clk	Diagnostic Word CRC32 Valid. This port reflects the validity of the CRC32 in the most recently received Diagnostic Word for the respective lane. A value of 1 indicated the CRC32 was valid and a value of 0 indicated the CRC32 was invalid. See section 5.4.6 of the Interlaken Protocol Definition, Revision 1.2
stat_rx_crc32_err[LANES-1:0]	O	clk	Diagnostic Word CRC32 Error/Invalid. This port provides an indication of an invalid CRC32 in the Diagnostic Word for the respective lane. These signals are asserted with a value of 1 for one LBUS clock cycle each time an error is detected.
stat_rx_fc_stat[MAX_CALLEN-1:0]	O	clk	RX Flow control Outputs. These signals indicate the flow control status for all of the calendar positions of the received data. A value of 1 means XON, a value of 0 means XOFF.
stat_rx_mubits[7:0]	O	clk	RX Multiple-Use Control Bits. This port contains the 'Multi-Use' field of the Interlaken Control (see the Interlaken Protocol specification). The values on the port are bits[31:24] of the most recently received Interlaken Control Word.
stat_rx_synced[LANES-1:0]	O	clk	Word Boundary Synchronized. These signals indicate whether a lane is word boundary synchronized. A value of 1 indicates the corresponding lane has achieved word boundary synchronization as follows: 64B/67B Word Boundary Locked, correctly receiving the Meta Frame, Synchronization Word, and correctly receiving the Scrambler State Control Word as described in sections 5.4.2, 5.4.3, and 5.4.4 of the Interlaken specification 1.2..
stat_rx_synced_err[LANES-1:0]	O	clk	Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective lane. A value of 1 indicates the corresponding lane had a word boundary synchronization error.
stat_rx_mf_len_err[LANES-1:0]	O	clk	Meta Frame Length Error. These signals indicate whether a Meta Frame length mismatch occurred in the respective lane. A value of 1 indicates the corresponding lane is receiving a Meta Frame of the wrong length.
stat_rx_mf_repeat_err[LANES-1:0]	O	clk	Meta Frame Consecutive Error. These signals indicate whether consecutive Meta Frame errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane.
stat_rx_descram_err[LANES-1:0]	O	clk	Scrambler State Control Word Error. These signals indicate a mismatch between the received Scrambler State Word and the expected value. A value of 1 indicates an error in the corresponding lane.
stat_rx_aligned	O	clk	All Lanes Aligned/De-Skewed. This signal indicates whether or not all lanes are aligned and de-skewed. A value of 1 indicates all lanes are aligned and de-skewed. When this signal is a 1, the RX path is aligned and can receive packet data.
stat_rx_aligned_err	O	clk	Loss of Lane Alignment/De-Skew. This signal indicates an error occurred during lane alignment or lane alignment was lost. A value of 1 indicates an error occurred.
stat_rx_err	O	clk	Control Word Error. This signal indicates whether a formatting error or a CRC24 error occurred in a Control Word. When operating in packet mode, this signal also indicates missing SOP or missing EOP errors. A value of 1 indicates an error occurred. Whenever this signal is asserted, all open packets are marked as containing errors as specified by the Interlaken Protocol Definition, Revision 1.2 . By definition, there is no mechanism provided by Interlaken to associate a CRC24 or similar error with individual packets. This signal is asserted for one clock period each time an error is detected.
stat_rx_overflow_err	O	clk	RX FIFO Overflow Error. This signal indicates if the LBUS interface is being clocked too slowly to properly receive the data being transmitted across the link. A value of 1 indicates an error occurred. In normal operation, this signal is always sampled as 0. If this signal is sampled as 1, the clocks are not set to proper frequencies and must be fixed.
stat_rx_mf_err[LANES-1:0]	O	clk	Meta Frame Synchronization Word Error. These signals indicate that an incorrectly formed Meta Frame Synchronization Word was detected in the respective lane. A value of 1 indicates an error occurred.
stat_rx_framing_err[LANES-1:0]	O	clk	Framing Error. These signals indicate that an illegal framing pattern was detected in the respective lane. A value of 1 indicates an error occurred.
stat_rx_msop_err	O	clk	Missing SOP Error. This signal indicates that a missing SOP was detected (and corrected).
stat_rx_meop_err	O	clk	Missing EOP Error. This signal indicates that a missing EOP was detected (and corrected).
stat_rx_burst_err	O	clk	Burst Error. This signal indicates that a BurstShort or a burst length error was detected.
stat_rx_misaligned	O	clk	Alignment Error. This signal indicates that the lane aligner did not receive the expected Meta Frame Synchronization Word across all (active) lanes. This signal can be used to collect the statistic "RX_Alignment_Error" as described in Table 5-9 of the Interlaken specification. This signal is not asserted until the Meta Frame Synchronization Word has been received at least once across all lanes. A value of 1 indicates the error occurred.
stat_rx_bad_type_err[LANES-1:0]	O	clk	Unexpected or Illegal Meta Frame Control Word Block Type. These signals indicate an unexpected or illegal Meta Frame Control Word Block Type was detected. These signals can be used to collect the statistic "RX_Bad_Control_Error" as described in Table 5-9 of the Interlaken specification. A value of 1 indicates an error in the corresponding lane.
stat_rx_mubits_updated	O	clk	RX Multiple-Use/General Purpose Control Bits Updated. This output indicates that `stat_rx_mubits` has been updated and is asserted for one clock cycle.
stat_rx_word_sync[LANES-1:0]	O	clk	64B/67B Word Boundary Locked. These signals indicate whether a lane is 64B/ 67B word boundary locked. A 64B/67B word boundary lock occurs if a lane detects 64 consecutive valid framing patterns on bits[65:64] as per the Interlaken Specification 1.2 Section 5.4.2. These signals are independent of both the Meta Frame Synchronization Word and Scrambler State Control Word. A value of 1 indicates the corresponding lane has achieved 64B/ 67B word boundary lock.

Port Descriptions - Port Descriptions - 1.2 English - PG209

Interlaken 600G LogiCORE IP Product Guide (PG209)