Performance and Resource Utilization - Performance and Resource Utilization - 1.2 English - PG209

Interlaken 600G LogiCORE IP Product Guide (PG209)
Document ID
PG209
Release Date
2025-08-29
Version
1.2 English

The following table provides approximate utilizations figures for some representative supported configurations when a single instance is instantiated in an AMD UltraScale™ device. These are estimated sizes only based on specific configurations and are subject to revision.

Note: Contact your AMD sales representative with your specific requirements.
Table 1. Device Utilization for Interlaken (UltraScale Series)
Interlaken Bandwidth Gb/s GTH/GTY Lanes Serial Transceiver Rate Gb/s LUT (1000s) FF (1000s) Block RAM LBUS Width Clk Freq
200 16 12.5 70 90 0 1,024 200
200 8 25 70 85 0 1,024 200
300 24 12.5 90 110 0 1,024 300
300 1 12 25 90 105 0 1,024 300
450 36 12.5 155 165 0 1,536 300
450 18 25 150 160 1 1,536 300
500 40 12.5 205 200 3 2,048 250
500 20 25 195 195 0 2,048 250
600 24 25 210 215 2 2,048 300
  1. See Appendix D, Interlaken 300G Core with Integrated Lane Logic for details on a 12x25.78125G solution with lower utilization by leveraging integrated lane logic.
  2. Resource utilization for Versal adaptive SoC devices is comparable to UltraScale Series devices.