Several issues can commonly occur during the first hardware test of an Interlaken IP core. These should be checked as indicated in the following steps.
It is assumed that the Interlaken IP core has already passed all simulation testing which is being implemented in hardware. This is a pre-requisite for any kind of hardware debug.
The usual sequence of debugging is to proceed in the following order:
- Clean up signal integrity.
- Ensure that each SerDes achieves clock data recovery (CDR) lock.
- Check that each lane has achieved word alignment.
- Check that lane alignment has been achieved.
- Proceed to Interface and Protocol debug.