The AMD Integrated Interlaken IP core is available in selected AMD UltraScale™ and AMD UltraScale+™ devices. It features a total bandwidth up to 150 Gb/s which supports up to 12 lanes at 12.5 Gb/s or up to 6 lanes at 25.78125 Gb/s.
The integrated Interlaken IP core supports protocol bypass (lane logic only) interface which provides direct user access to the lane logic function. This allows you to build a fully featured Interlaken core by leveraging existing integrated lane logic and soft protocol logic.
On AMD Virtex™ UltraScale+™ devices, all 12 lanes of the Integrated Interlaken core support up to 25.78125 Gb/s line rate in protocol bypass (lane logic only) mode. Therefore, integrated lane logic can be used along with AMD soft Interlaken protocol logic to build an Interlaken core with overall bandwidth of up to 300 Gb/s. By leveraging integrated lane logic, this solution has lower resource utilization compared to a fully soft 300G Interlaken core.
The 300 Gb/s Interlaken core with integrated lane logic has the following features:
- 12 lanes x 25.78125 Gb/s
- 1024-bit segmented LBUS user interface
- 412 MHz LBUS clock rate
- 64-bit interface to serial GTY transceivers
- Typical device utilization of 53K LUTs
- Support for Virtex UltraScale+ devices
The following figure presents the upper levels of hierarchy for the 300G Interlaken core with integrated lane logic.