| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD Virtex™ UltraScale+™ AMD Kintex™ UltraScale+™ AMD Zynq™ UltraScale+ ™ AMD Virtex™ UltraScale™ AMD Kintex™ UltraScale™ AMD Versal™ Adaptive SoC |
| Supported User Interfaces | Segmented LBUS |
| Resources | Table 1 |
| Provided with Core | |
| Design Files | EDF |
| Example Design | Verilog |
|
Instantiation Template |
Verilog |
| Test Bench | Verilog Test Bench |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Verilog |
| Supported S/W Driver | Not Applicable |
| Tested Design Flows 2 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation |
Mentor Graphics Questa Advanced Simulator Synopsys VCS Cadence Incisive |
| Synthesis | Vivado |
| Support | |
| Release Notes and Known Issues | Master Answer Record:N/A |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| AMD Adaptive SoC & FPGA Support web page | |
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