The Interlaken 600G IP core is delivered as a soft macro block. The upper levels of hierarchy are shown in following figure. The text in the figure represents the name of the module at that level of hierarchy. The instance name is in parentheses.
One of the benefits of the Interlaken 600G core is the ability to use any number of serial lanes for an aggregate bandwidth of up to 600 Gb/s. For AMD FPGA platform-specific information, see the AMD website. For more information, see the Interlaken Protocol Definition, Revision 1.2.
This product guide describes the Interlaken 600G IP core in detail and provides the information required to integrate the Interlaken 600G IP core into your designs. The document assumes familiarity with the Interlaken protocol and the FPGA design and methodology.
The interlaken_top module contains
instantiations of the receive and transmit serial transceiver macros to allow for
testing and simulation of the Interlaken 600G IP
core. The connections to/from the serial transceiver macros in the interlaken_top module must only be used as a reference.
You must instantiate the appropriate serial transceiver and make the proper connections
to the interlaken_cores modules.
The interlaken_cores module contains all of the logic for the Interlaken 600G IP core. It is divided into two submodules:
tx_core and rx_core. Instantiate
interlaken_cores when using the Interlaken 600G IP core in duplex mode, or instantiate the tx_core and
rx_core separately when using the Interlaken 600G IP core in simplex mode. See Appendix F, Additional Resources and Legal Notices
for a list of transceiver user guides.