- Support for data rates up to 600 Gb/s
- Support for any serial data rate including 25 Gb/s serial transceiver and above
- Flexible serial transceiver interface to accommodate different I/O implementations
- Data striping and de-striping across multiple lanes. The number of lanes is limited only by the available FPGA resources
- Programmable BurstMax, BurstShort and MetaFrameSize parameters
- 64/67 encoding and decoding
- Automatic word and lane alignment
- Self-synchronizing data scrambler
- Data bus width of 1024, 1536, or 2048 bits
- CRC24 and CRC32 generation and checking for burst and lane data integrity
See Feature Summary in Chapter 2 for more features.