Example Wrapper Clocking for a Synchronous System - Example Wrapper Clocking for a Synchronous System - 1.2 English - PG209

Interlaken 600G LogiCORE IP Product Guide (PG209)

Document ID
PG209
Release Date
2025-08-29
Version
1.2 English

In a synchronous system, rx_serdes_clk and tx_serdes_refclk can use the same clock. TXOUTCLK from one transceiver is sent to a Mixed-Mode Clock Manager (MMCM), which generates the RX and TX userclks for all of the transceivers and for the rx_serdes_clk and tx_serdes_refclk in the Interlaken 600G core.