The Interlaken 600G IP core is delivered as a soft macro block, which allows implementation of the core in the following target devices with minimal effort. “Minimal effort” means you can instantiate the core as a black box in your design.
- AMD Virtex™ UltraScale+™ FPGAs
- AMD Kintex™ UltraScale+™ FPGAs
- AMD Virtex™ UltraScale™ FPGAs
- AMD Kintex™ UltraScale™ FPGAs
- AMD Zynq™ UltraScale+™ MPSoCs
- AMD Versal™ Adaptive SoC
To implement the core, connect the Interlaken 600G IP core to the high-speed serial transceiver blocks, provide the appropriate clock signals, and connect to the Local Bus (LBUS) user-side interface.