Clocking - Clocking - 1.2 English - PG209

The Interlaken 600G IP core has the following major clock domains:

LBUS Interface

This clock drives logic for both the RX and TX LBUS interfaces and the protocol layer processing.

RX Serial Transceiver Domain

Each serial transceiver lane has its own recovered clock. This clock is used for all of the logic for that serial transceiver lane. The Interlaken 600G IP core synchronizes the received data from all of the serial transceivers to the LBUS clock domain.

TX Serial Transceiver Domain

The TX serial transceiver domain consists of logic that is operated on the clock domain associated with each TX serial transceiver macro. All of the serial transceiver macros must be clocked using the same reference clock source to ensure frequency matching between the lanes.

The following figure shows the different clock domains in the RX direction along with their associated clock inputs.

Figure 1. RX Clock Domains

The Following figure shows the different clock domains in the TX direction along with their associated clock inputs. The core handles all clock domain crossings

Figure 2. TX Clock Domains

The clk input port is used to clock the protocol processing of the Interlaken 600G IP core. This includes all logic in the TX and RX paths responsible for Control Word processing, Meta Frame processing, and the LBUS interface.

The frequency of the clk domain must be high enough to handle the overall bit rate of the serial link. The following equation is used to estimate the minimum clk frequency:

clk frequency >(number_of_lanes × serial_bit_rate)/(internal_bus_width)

As an example, if there are 18 serial lanes with each lane running at 25 Gb/s and a 1,536-bit internal bus, the minimum clk frequency is (18 × 25 Gb/s/1536) = 293 MHz.