Data must be written to the TX LBUS such that there are no overflow or underflow conditions. LBUS bandwidth must always be greater than the Interlaken bandwidth to guarantee that bursts can be sent without interruption.
When writing data to the LBUS, the tx_rdyout signal must always be
observed. This signal indicates whether the fill level of the TX buffer is within an
acceptable range or not. If this signal is ever asserted, you must stop writing to
the TX LBUS until the signal is deasserted. Because the TX LBUS has greater
bandwidth than the TX Interlaken interface, it is not unusual to see this signal
being frequently asserted and this is not a cause for concern. You must ensure that
TX writes are stopped when tx_rdyout is asserted.
tx_rdyout becomes asserted is determined by the
bus ctl_tx_rdyout_thresh. It might be necessary to adjust this bus
as required to ensure that your transmitting protocol is able to handle the
tx_rdyout requirement.tx_rdyout is ignored, the signal
tx_ovfout might be asserted, indicating a buffer overflow.
This must not be allowed to occur. AMD recommends that
the Interlaken IP core be reset if tx_ovfout is ever asserted.
Do not attempt to continue debugging after tx_ovfout has been
asserted until the cause of the overflow has been addressed.If stat_tx_underflow_err is ever asserted, debugging must stop until
the condition that caused the underflow is addressed. This can happen if the core
clock is not fast enough to supply the transceiver with data, and you should ensure
that the minimum core clock frequency is being observed. This can happen if the core
clock is not fast enough to supply the transceiver with data, and you should ensure
that the minimum core clock frequency is being observed.