The AMD UltraScale™ /AMD UltraScale+™ GTH Quad provides more flexibility than the 7 series GTX Quad. The AMD UltraScale™ /AMD UltraScale+™ GTH Quad has two QPLLs and four CPLLs, one CPLL for each transceiver. For full flexibility, one QPLL is given a 148.5 MHz reference clock and the other QPLL is given a 148.5/1.001 MHz reference clock as shown in the following figure. The clocks from both QPLLs are routed to each RX and TX unit in the quad. Each RX and TX unit can independently select the clock from either QPLL and then divide that clock by 1, 2, 4, or 8. This allows full independence of all RX units and TX units in the quad to run at any SDI line rate. Both the 11.88 Gb/s and 11.88/1.001 Gb/s line rates can be simultaneously supported in the same quad.
The receivers can use just one QPLL for all line rates except in the case of 12G-SDI, where the receivers must use the correct QPLL for the particular 12G-SDI line rate to be supported. The TX units must dynamically switch between the two QPLLs based on which line rate they need to transmit. In such a case, the CPLLs are not needed.
For UltraScale+ devices, when using QPLL0 and QPLL1 for the 12G-SDI integer and fraction (1/1.001) rate, switching between rates on the SDI-RX can introduce a glitch on the clock which causes CRC errors on the TX channel. CRC errors do not occur in SDI-SDI/HD-SDI/3-G SDI/6-GSDI integer/fractional modes with a QPLL0 and QPLL1 clocking combination. For more details, see Answer Record 72254 and 72449.
Therefore, it is not recommended to use this clocking configuration when both the transmit and receive 12G-SDI integer and fractional modes use the same transceiver. The integer and fractional rates for TX can be selected using a CPLL reference clock input selection with 297 MHz and 296.7 MHz respectively. This CPLL/QPLL clocking combination is not feasible with -1 speed grade devices because the CPLL does not support the 12G-SDI line rate. You need to select a UltraScale+ GTY/GTH -2 speed grade or faster rate with >0.85 V.
Refer to the SMPTE UHD-SDI Receiver Subsystem Product Guide (PG290) for further explanation and an audio video loopback example design implemented using a CPLL/QPLL combination targeting a KCU116 board.